Data Sheet
26185.1
10E
A6832
DABiC-5 32-Bit Serial Input Latched Sink Drivers
Intended originally to drive thermal printheads, the A6832 has been
optimized for low output-saturation voltage, high-speed operation,
and pin confi gurations that are the most convenient for the tight space
requirements of high-resolution printheads. These integrated circuits
can also be used to drive multiplexed LED displays or incandescent
lamps at up to 125 mA peak current. The combination of bipolar and
MOS technologies gives the A6832 arrays an interface fl exibility
beyond the reach of standard buffers and power driver circuits.
The devices each have 32 bipolar npn open-collector saturated driv-
ers, a CMOS data latch for each of the drivers, two 16-bit CMOS shift
registers, and CMOS control circuitry. The high-speed CMOS shift reg-
isters and latches allow operation with most microprocessor-based sys-
tems. Use of these drivers with TTL may require input pull-up resistors
to ensure an input logic high. MOS serial data outputs permit cascading
for interface applications requiring additional drive lines.
The A6832 is supplied in a 44-lead plastic leaded chip carrier (package
suffi x EP), for surface-mount applications requiring minimum area. These
devices are lead (Pb) free, with 100% matte tin plated leadframes.
3.3 V to 5 V logic supply range
To 10 MHz data input rate
Schmitt trigger inputs for improved noise immunity
Low-power CMOS logic and latches
40 V current sink outputs
Low saturation voltage
40C operation available
Use the following complete part numbers when ordering:
AB SO LUTE MAX I MUM RAT INGS
Part Number
Pins
Package
Operating Temperature
A6832SEP-T
44
PLCC
20C to +85C
A6832EEP-T
44
PLCC
40C to +85C
Output Voltage, V
OUT
.........................................40 V
Logic Supply Voltage, V
DD
...................................7 V
Input Voltage Range, V
IN
..............0.3 V to V
DD
+0.3 V
Continuous Output Current, I
OUT
................. 125 mA
Package Power Dissipation, P
D
, see chart, page 5
Operating Temperature Range
Ambient Temperature, T
A
............20C to +85C
Storage Temperature, T
S
..........55C to +150C
Caution: CMOS devices have input-static protection,
but are susceptible to damage when exposed to
extremely high static-electrical charges.
FEATURES
Thermal printheads
Multiplexed LED displays
Incandescent lamps
APPLICATIONS
A6832SEP/A6832EEP
44-pin PLCC
12
13
14
15
16
17
10
11
9
8
7
27
26
25
24
23
22
21
28
20
19
18
35
34
33
32
31
36
37
38
39
29
2
1
44
43
42
3
4
5
6
40
41
30
2
Worcester, Massachusetts 01615-0036 (508) 853-5000
115 Northeast Cutoff, Box 15036
www.allegromicro.com
A6832
DABiC-5 32-Bit Serial-Input Latched Sink Drivers
Data Sheet
26185.1
10E
Functional Block Diagram
32-B IT S HIF T R E G IS T E R
LAT C HE S
C LOC K
S E R IAL
DATA IN
S T R OB E
OUT P UT
E NAB LE
V
DD
S E R IAL DATA
OUT
MOS
B IP OLAR
OUT
OUT
OUT
OUT
OUT
OUT
1
2
3
30
31
32
G R OUND
Typical Input Circuit
Typical Output Driver
IN
V
DD
OUT
V
DD
3
Worcester, Massachusetts 01615-0036 (508) 853-5000
115 Northeast Cutoff, Box 15036
www.allegromicro.com
A6832
DABiC-5 32-Bit Serial-Input Latched Sink Drivers
Data Sheet
26185.1
10E
ELECTRICAL CHARACTERISTICS
1
Unless otherwise noted: T
A
= 25C, logic supply operating voltage V
dd
= 3.0 V to 5.5 V
Characteristic
Symbol
Test Conditions
V
dd
= 3.3 V
V
dd
= 5 V
Units
Min.
Typ. Max.
Min.
Typ.
Max.
Output Leakage Current
I
CEX
V
OUT
= 40 V
10
10
A
CollectorEmitter
Saturation Voltage
V
CE(SAT)
I
OUT
= 50 mA
275
275
mV
I
OUT
= 100 mA
550
550
mV
Input Voltage
V
IN(1)
2.2
3.3
V
V
IN(0)
1.1
1.7
V
Input Current
I
IN(1)
V
IN
= V
DD
< 0.01
1.0
< 0.01
1.0
A
I
IN(0)
V
IN
= 0 V
< 0.01
1.0
< 0.01
1.0
A
Serial Data Output Voltage
V
OUT(1)
I
OUT
= 200 A
2.8
3.05
4.5
4.75
V
V
OUT(0)
I
OUT
= 200 A
0.15
0.3
0.15
0.3
V
Maximum Clock Fre-
quency
2
f
c
10
10
MHz
Logic Supply Current
I
DD(1)
One output on, I
OUT
= 100 mA
6.0
6.0
mA
I
DD(0)
All outputs off
100
100
A
Output Enable-to-Output
Delay
t
dis(BQ)
V
CC
= 50 V, R1 = 500 , C1 30 pF
1.0
1.0
s
t
en(BQ)
V
CC
= 50 V, R1 = 500 , C1 30 pF
1.0
1.0
s
Strobe-to-Output Delay
t
p(STH-QL)
V
CC
= 50 V, R1 = 500 , C1 30 pF
1.0
1.0
s
t
p(STH-QH)
V
CC
= 50 V, R1 = 500 , C1 30 pF
1.0
1.0
s
Output Fall Time
t
f
V
CC
= 50 V, R1 = 500 , C1 30 pF
1.0
1.0
s
Output Rise Time
t
r
V
CC
= 50 V, R1 = 500 , C1 30 pF
1.0
1.0
s
Clock-to-Serial Data Out Delay
t
p(CH-SQX)
I
OUT
= 200 A
50
50
ns
1
Positive (negative) current is defi ned as conventional current going into (coming out of) the specifi ed device pin.
2
Operation at a clock frequency greater than the specifi ed minimum value is possible but not warran
teed.
L = Low Logic Level
H = High Logic Level
X = Irrelevant
P = Present State
R = Previous State
Serial
Shift Register Contents
Serial
Latch Contents
Output Output Contents
Data
Clock
Data
Strobe
Enable
Input
Input I
1
I
2
I
3
...
I
N-1
I
N
Output
Input
I
1
I
2
I
3
...
I
N-1
I
N
Input
I
1
I
2
I
3
... I
N-1
I
N
H
H
R
1
R
2
...
R
N-2
R
N-1
R
N-1
L
L
R
1
R
2
...
R
N-2
R
N-1
R
N-1
X
R
1
R
2
R
3
...
R
N-1
R
N
R
N
X
X
X
...
X
X
X
L
R
1
R
2
R
3
...
R
N-1
R
N
P
1
P
2
P
3
...
P
N-1
P
N
P
N
H
P
1
P
2
P
3
...
P
N-1
P
N
H
P
1
P
2
P
3
... P
N-1
P
N
X
X
X
...
X
X
L
H
H
H
... H H
Truth Table
4
Worcester, Massachusetts 01615-0036 (508) 853-5000
115 Northeast Cutoff, Box 15036
www.allegromicro.com
A6832
DABiC-5 32-Bit Serial-Input Latched Sink Drivers
Data Sheet
26185.1
10E
Timing Requirements and Specifi cations
(Logic Levels are V
DD
and Ground)
C LOC K
S E R IAL
DAT A IN
S T R OB E
OUT P UT E NAB LE
OUT
N
50%
S E R IAL
DAT A OUT
DAT A
DAT A
10%
90%
50%
50%
50%
C
A
B
D
E
HIG H = ALL OUT P UT S E NAB LE D
p(S T H-QL)
t
p(C H-S QX)
t
DAT A
p(S T H-QH)
t
OUT P UT E NAB LE
OUT
N
DAT A
10%
50%
dis (B Q)
t
en(B Q)
t
LOW = ALL OUT P UT S B LANK E D (DIS AB LE D)
r
t
f
t
50%
90%
NOTE: Timing is representative of a 10 MHz clock. Higher speeds
may be attainable; operation at high temperatures will reduce the
specifi ed maximum clock frequency.
S
erial Data present at the input is transferred to the shift register on
the logical 0 to logical 1 transition of the CLOCK input pulse. On
succeeding CLOCK pulses, the registers shift data information towards
the SERIAL DATA OUTPUT. The SERIAL DATA must appear at the
input prior to the rising edge of the CLOCK input waveform.
Information present at any register is transferred to the respective
latch when the STROBE is high (serial-to-parallel conversion). The
latches will continue to accept new data as long as the STROBE is
held high. Applications where the latches are bypassed (STROBE
tied high) will require that the OUTPUT ENABLE input be low
during serial data entry.
When the OUTPUT ENABLE input is low, the output sink drivers
are disabled (OFF). The information stored in the latches is not
affected by the OUTPUT ENABLE input. With the OUTPUT
ENABLE input high, the outputs are controlled by the state of their
respective latches.
Key
Description
Symbol
Time (ns)
A
Data Active Time Before Clock Pulse (Data Set-Up Time)
t
su(D)
25
B
Data Active Time After Clock Pulse (Data Hold Time)
t
h(D)
25
C
Clock Pulse Width
t
w(CH)
50
D
Time Between Clock Activation and Strobe
t
su(C)
100
E
Strobe Pulse Width
t
w(STH)
50
5
Worcester, Massachusetts 01615-0036 (508) 853-5000
115 Northeast Cutoff, Box 15036
www.allegromicro.com
A6832
DABiC-5 32-Bit Serial-Input Latched Sink Drivers
Data Sheet
26185.1
10E
1
4
5
6
18
19
20
21
22
23
24
25
26
27
28
40
41
42
43
44
2
3
7
8
9
10
11
12
13
14
15
16
17
OUT
NC
STROBE
1
GROUND
SERIAL
DA
T
A
IN
LOGIC
SUPPL
Y
CLOCK
SERIAL
DA
T
A
OUT
OUTPUT
ENABLE
NC
OUT
32
38
39
37
36
35
34
33
32
31
30
29
OUT
31
OUT
21
NC
OUT
13
OUT
16
IC
OUT
17
O
UT
20
NC
V
DD
32
SHIFT
REGISTER
LA
TCHES
SHIFT
REGISTER
LA
TCHES
OUT
12
OUT
2
A6832SEP/A6832EEP
50
75
100
125
150
PACKAGE
POWER
DISSIPATION
(
W)
AMBIENT TEMPERATURE ( C)
25
4.0
3.0
3.5
0.5
0
2.5
2.0
1.5
1.0
4.5
A6832EP, R
= 54 C/W
JA
A6832EP, R
= 30 C/W
JA
Allowable Power Dissipation, P
D
*
*Additional thermal information is available on the Allegro Web site.
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