Data Sheet
26185.1
16B
A6833
DABiC-5 32-Bit Serial Input Latched Sink Drivers
Designed to reduce logic supply current, chip size, and system cost, the
A6833 integrated circuits offer high-speed operation for thermal print-
ers. These devices can also be used to drive multiplexed LED displays
or incandescent lamps within their 125 mA peak output current rating.
The combination of bipolar and MOS technologies gives the A6833
smart power ICs an interface flexibility beyond the reach of standard
buffers and power driver circuits.
These 32-bit drivers have bipolar open-collector npn Darlington out-
puts, a CMOS data latch for each of the drivers, a 32-bit CMOS shift
register, and CMOS control circuitry. The high-speed CMOS shift
registers and latches allow operation with most microprocessor-based
systems. Use of these drivers with TTL may require input pull-up resis-
tors to ensure an input logic high. CMOS serial data outputs permit
cascading for applications requiring additional drive lines.
The A6833 is supplied in a 44-lead plastic chip carrier (quad pack),
intended for surface mounting on solder lands with 0.050 in. (1.27 mm)
centers. These devices are lead (Pb) free, with 100% matte tin plated
leadframes.
3.3 V to 5 V logic supply range
To 10 MHz data input rate
30 V minimum output breakdown
Darlington current-sink outputs
Low-power CMOS logic and latches
Schmitt trigger inputs for improved noise immunity
Use the following complete part numbers when ordering:
AB SO LUTE MAX I MUM RAT INGS
Part Number
Pins
Package
A6833SEP-T
44
PLCC
Output Voltage, V
OUT
.........................................30 V
Logic Supply Voltage, V
DD
...................................7 V
Input Voltage Range, V
IN
..............0.3 V to V
DD
+0.3 V
Continuous Output Current (each output), I
OUT
... 125 mA
Package Power Dissipation, P
D
A6833SA................................................ 3.5 W*
A6833SEP.............................................. 2.5 W*
Operating Temperature Range
Ambient Temperature, T
A
............20C to +85C
Storage Temperature, T
S
..........55C to +150C
*Derate linearly to 0 W at +150C.
Caution: CMOS devices have input-static protection,
but are susceptible to damage when exposed to
extremely high static-electrical charges.
FEATURES
Thermal printheads
Multiplexed LED displays
Incandescent lamps
APPLICATIONS
A6833SEP
44-pin PLCC
12
13
14
15
16
17
10
11
9
8
7
27
26
25
24
23
22
21
28
20
19
18
35
34
33
32
31
36
37
38
39
29
2
1
44
43
42
3
4
5
6
40
41
30
2
Worcester, Massachusetts 01615-0036 (508) 853-5000
115 Northeast Cutoff, Box 15036
www.allegromicro.com
A6833
DABiC-5 32-Bit Serial-Input Latched Sink Drivers
Data Sheet
26185.1
16B
Functional Block Diagram
32-B IT S HIF T R E G IS T E R
LAT C HE S
C LOC K
S E R IAL
DATA IN
S T R OB E
OUT P UT
E NAB LE
V
DD
S E R IAL DATA
OUT
MOS
B IP OLAR
OUT
OUT
OUT
OUT
OUT
OUT
1
2
3
30
31
32
G R OUND
P OW E R
S UB
LOG IC
G R OUND
Typical Input Circuit
Typical Output Driver
IN
V
DD
SUB
OUT
3
Worcester, Massachusetts 01615-0036 (508) 853-5000
115 Northeast Cutoff, Box 15036
www.allegromicro.com
A6833
DABiC-5 32-Bit Serial-Input Latched Sink Drivers
Data Sheet
26185.1
16B
ELECTRICAL CHARACTERISTICS
1
Unless otherwise noted: T
A
= 25C, logic supply operating voltage V
dd
= 3.0 V to 5.5 V
Characteristic
Symbol
Test Conditions
V
dd
= 3.3 V
V
dd
= 5 V
Units
Min.
Typ. Max. Min.
Typ.
Max.
Output Leakage Current
I
CEX
V
OUT
= 30 V
10
10
A
CollectorEmitter Saturation
Voltage
V
CE(SAT)
I
OUT
= 50 mA
0.7
0.7
V
I
OUT
= 100 mA
1.0
1.0
V
Input Voltage
V
IN(1)
2.2
3.3
V
V
IN(0)
1.1
1.7
V
Input Current
I
IN(1)
V
IN
= V
DD
< 0.01
1.0
< 0.01
1.0
A
I
IN(0)
V
IN
= 0 V
< 0.01
1.0
< 0.01
1.0
A
Serial Data Output Voltage
V
OUT(1)
I
OUT
= 200 A
2.8
3.05
4.5
4.75
V
V
OUT(0)
I
OUT
= 200 A
0.15
0.3
0.15
0.3
V
Maximum Clock Frequency
2
f
c
10
10
MHz
Logic Supply Current
I
DD(1)
One output on, I
OUT
= 100 mA
2.0
2.0
mA
I
DD(0)
All outputs off
100
100
A
Output Enable-to-Output Delay
t
dis(BQ)
V
CC
= 50 V, R1 = 500 , C1 30 pF
1.0
1.0
s
t
en(BQ)
V
CC
= 50 V, R1 = 500 , C1 30 pF
1.0
1.0
s
Strobe-to-Output Delay
t
p(STH-QL)
V
CC
= 50 V, R1 = 500 , C1 30 pF
1.0
1.0
s
t
p(STH-QH)
V
CC
= 50 V, R1 = 500 , C1 30 pF
1.0
1.0
s
Output Fall Time
t
f
V
CC
= 50 V, R1 = 500 , C1 30 pF
500
500
ns
Output Rise Time
t
r
V
CC
= 50 V, R1 = 500 , C1 30 pF
500
500
ns
Clock-to-Serial Data Out Delay
t
p(CH-SQX)
I
OUT
= 200 A
50
50
ns
1
Positive (negative) current is defined as conventional current going into (coming out of) the specified device pin.
2
Operation at a clock frequency greater than the specified minimum value is possible but not warran
teed.
L = Low Logic Level
H = High Logic Level
X = Irrelevant
P = Present State
R = Previous State
Serial
Shift Register Contents
Serial
Latch Contents
Output Output Contents
Data
Clock
Data
Strobe
Enable
Input
Input I
1
I
2
I
3
...
I
N-1
I
N
Output
Input
I
1
I
2
I
3
...
I
N-1
I
N
Input
I
1
I
2
I
3
... I
N-1
I
N
H
H
R
1
R
2
...
R
N-2
R
N-1
R
N-1
L
L
R
1
R
2
...
R
N-2
R
N-1
R
N-1
X
R
1
R
2
R
3
...
R
N-1
R
N
R
N
X
X
X
...
X
X
X
L
R
1
R
2
R
3
...
R
N-1
R
N
P
1
P
2
P
3
...
P
N-1
P
N
P
N
H
P
1
P
2
P
3
...
P
N-1
P
N
H
P
1
P
2
P
3
... P
N-1
P
N
X
X
X
...
X
X
L
H
H
H
... H H
Truth Table
4
Worcester, Massachusetts 01615-0036 (508) 853-5000
115 Northeast Cutoff, Box 15036
www.allegromicro.com
A6833
DABiC-5 32-Bit Serial-Input Latched Sink Drivers
Data Sheet
26185.1
16B
Timing Requirements and Specifications
(Logic Levels are V
DD
and Ground)
C LOC K
S E R IAL
DAT A IN
S T R OB E
OUT P UT E NAB LE
OUT
N
50%
S E R IAL
DAT A OUT
DAT A
DAT A
10%
90%
50%
50%
50%
C
A
B
D
E
HIG H = ALL OUT P UT S E NAB LE D
p(S T H-QL)
t
p(C H-S QX)
t
DAT A
p(S T H-QH)
t
OUT P UT E NAB LE
OUT
N
DAT A
10%
50%
dis (B Q)
t
en(B Q)
t
LOW = ALL OUT P UT S B LANK E D (DIS AB LE D)
r
t
f
t
50%
90%
NOTE: Timing is representative of a 10 MHz clock. Higher speeds
may be attainable; operation at high temperatures will reduce the
specified maximum clock frequency.
S
erial Data present at the input is transferred to the shift register on
the logical 0 to logical 1 transition of the CLOCK input pulse. On
succeeding CLOCK pulses, the registers shift data information towards
the SERIAL DATA OUTPUT. The SERIAL DATA must appear at the
input prior to the rising edge of the CLOCK input waveform.
Information present at any register is transferred to the respective
latch when the STROBE is high (serial-to-parallel conversion). The
latches will continue to accept new data as long as the STROBE is
held high. Applications where the latches are bypassed (STROBE
tied high) will require that the OUTPUT ENABLE input be low
during serial data entry.
When the OUTPUT ENABLE input is low, the output sink drivers
are disabled (OFF). The information stored in the latches is not
affected by the OUTPUT ENABLE input. With the OUTPUT
ENABLE input high, the outputs are controlled by the state of their
respective latches.
Key
Description
Symbol
Time (ns)
A
Data Active Time Before Clock Pulse (Data Set-Up Time)
t
su(D)
25
B
Data Active Time After Clock Pulse (Data Hold Time)
t
h(D)
25
C
Clock Pulse Width
t
w(CH)
50
D
Time Between Clock Activation and Strobe
t
su(C)
100
E
Strobe Pulse Width
t
w(STH)
50
5
Worcester, Massachusetts 01615-0036 (508) 853-5000
115 Northeast Cutoff, Box 15036
www.allegromicro.com
A6833
DABiC-5 32-Bit Serial-Input Latched Sink Drivers
Data Sheet
26185.1
16B
1
4
5
6
18
19
20
21
22
23
24
25
26
27
28
40
41
42
43
44
2
3
7
8
9
10
11
12
13
14
15
16
17
OUT
2
OUT
3
OUT
4
OUT
5
OUT
6
OUT
7
OUT
8
OUT
9
OUT
OUT
10
OUT
11
12
OUT
NC
STROBE
1
POWER GROUND
SERIAL
DA
T
A
IN
LOGIC
SUPPL
Y
CLOCK
SERIAL
DA
T
A
OU
T
OUTPUT
ENABLE
NC
OUT
32
38
39
37
36
35
34
33
32
31
30
29
OUT
31
OUT
30
OUT
29
OUT
28
OUT
27
OUT
26
OUT
25
OUT
24
OUT
23
OUT
22
OUT
21
NC
OUT
13
OUT
14
OUT
15
OUT
16
LOGIC GROUND
OUT
17
OUT
18
OUT
19
OUT
20
NC
SUB
REGISTER
REGISTER
LA
TCHES
LA
TCHES
ST
CLK
OE
V
DD
A6833SEP
6
Worcester, Massachusetts 01615-0036 (508) 853-5000
115 Northeast Cutoff, Box 15036
www.allegromicro.com
A6833
DABiC-5 32-Bit Serial-Input Latched Sink Drivers
Data Sheet
26185.1
16B
Dimensions in Inches
(controlling dimensions)
Dimensions in Millimeters
(for reference only)
Dwg. MA-005-44A mm
17.65
17.40
0.51
MIN
4.57
4.20
17.65
17.40
16.662
16.510
1.27
BSC
0.812
0.661
1
44
0.533
0.331
INDEX AREA
2
28
29
39
40
6
7
17
18
16.662
16.510
8.10
7.39
8.10
7.39
18
28
Dwg. MA-005-44A in
0.020
MIN
0.050
BSC
1
44
0.021
0.013
INDEX AREA
2
6
7
17
29
39
40
0.695
0.685
0.032
0.026
0.319
0.291
0.319
0.291
0.180
0.165
0.695
0.685
0.656
0.650
0.656
0.650
NOTES: 1. Exact body and lead configuration at vendor's option within limits shown.
2. Lead spacing tolerance is non-cumulative.
A6833SEP
7
Worcester, Massachusetts 01615-0036 (508) 853-5000
115 Northeast Cutoff, Box 15036
www.allegromicro.com
A6833
DABiC-5 32-Bit Serial-Input Latched Sink Drivers
Data Sheet
26185.1
16B
The products described here are manufactured under one or
more U.S. patents or U.S. patents pending.
Allegro MicroSystems, Inc. reserves the right to make, from time
to time, such de par tures from the detail spec i fi ca tions as may be
required to permit improvements in the per for mance, reliability,
or manufacturability of its products. Before placing an order, the
user is cautioned to verify that the information being relied upon is
current.
Allegro products are not authorized for use as critical compo-
nents in life-support devices or sys tems without express written
approval.
The in for ma tion in clud ed herein is believed to be ac cu rate and
reliable. How ev er, Allegro MicroSystems, Inc. assumes no re spon -
si bil i ty for its use; nor for any in fringe ment of patents or other
rights of third parties which may result from its use.
Copyright2003, 2004, 2005 AllegroMicrosystems, Inc.
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