The SLA7042M and SLA7044M are designed for high-efficiency

and high-performance microstepping operation of 2-phase, unipolar
stepper motors. Microstepping provides improved resolution without
limiting step rates, and provides much smoother low-speed motor
operation. An automated, innovative packaging technology combined
with power NMOS FETs and monolithic CMOS logic/control circuitry
advances power multi-chip modules (PMCMsTM) toward the complete
integration of motion control. Each half of these stepper motor control-
ler/drivers operate independently. The 4-bit shift registers are serially
loaded with motor phase information and output current-ratio data (eight
levels). The combination of user-selectable current-sensing resistor,
linearly adjustable reference voltage, and digitally selected output
current ratio provides users with a broad, variable range of of full, half,
and microstepping motor control (I

OUT

REF

/3 · R

] · Current Ratio).

Each PMCM is rated for a maximum motor supply voltage of 46 V

and utilizes advanced NMOS FETs for the high-current, high-voltage
driver outputs. The avalanche-rated (

100 V) FETs provide excellent

ON resistance, improved body diodes, and very-fast switching. The
multi-chip ratings and performance afford significant benefits and
advantages for stepper drives when compared to the higher dissipation
and slower switching speeds associated with bipolar transistors. Highly
automated manufacturing techniques provide low-cost and exception-
ally reliable PMCMs suitable for controlling and directly driving a broad
range of 2-phase, unipolar stepper motors. The SLA7042M and
SLA7044M are identical except for r

DS(on)

and output current ratings.

Complete applications information is given on the following pages.

PWM current is regulated by appropriately choosing current-sensing
resistors, a voltage reference, and digitally programmable current ratio.
Inputs are compatible with 5 V logic and microprocessors.

BENEFITS AND FEATURES

Cost-Effective, Multi-Chip Solution

`Turn-Key' Motion-Control Module

Motor Operation to 3 A and 46 V

Generation High-Voltage FETs

100 V, Avalanche-Rated NMOS

Low r

DS(on)

NMOS Outputs

Advanced, Improved Body Diodes

Microstepping Unipolar Drive

High-Efficiency, High-Speed PWM

MICROSTEPPING, UNIPOLAR PWM,

HIGH-CURRENT MOTOR CONTROLLER/DRIVER

Always order by complete part number: SLA7042M .

Data Sheet

28202A*

REF/ENABLE A

REF

Dwg. PK-008

OUT A

OUT B

SENSEA

GROUND A

CNTRL SPLY A

REF

OUTA

CONTROL/LOGIC

OUT B

GROUND B

REF/ENABLE B

CNTRL SPLY B

SERIAL DATA A

CLOCK A

SERIAL DATA B

CLOCK B

SENSE B

STROBEA

STROBE B

SR/LATCH

D/A

CONTROL/LOGIC

SR/LATCH

D/A

ABSOLUTE MAXIMUM RATINGS

at T

= +25

Load Supply Voltage, V

. . . . . . . . . . . . 46 V

FET Output Voltage, V

. . . . . . . . . . . 100 V

Control Supply Voltage, V

. . . . . . . . . 7.0 V

Peak Output Current,

OUTM

s) . . . . . . . . . . . . . . . . 5.0 A

Continuous Output Current, I

OUT

SLA7042M . . . . . . . . . . . . . . . . . . . . . 1.5 A

SLA7044M . . . . . . . . . . . . . . . . . . . . . 3.0 A

Input Voltage Range,

. . . . . . . . . . . . . . -0.3 V to V

+ 0.3 V

Reference Voltage, V

REF

. . . . . . . . . . . . V

Package Power Dissipation, P

. See Graph

Junction Temperature, T

. . . . . . . . . +150

Operating Temperature Range,

. . . . . . . . . . . . . . . . . . . . -20

C to +85

Storage Temperature Range,

stg

. . . . . . . . . . . . . . . . . . -40

C to +150

Independent PWM Current Control

(2-Phase)

Digitally Programmable PWM

Current Control

Low Component-Count PWM Drive

Low Internal-Power Dissipation

Electrically Isolated Power Tab

Logic IC- and

P-Compatible

Inputs

Machine-Insertable Package

SLA7042M

AND

SLA7044M

SLA7042M

AND

SLA7044M

MICROSTEPPING,
UNIPOLAR PWM, HIGH-CURRENT
MOTOR CONTROLLER/DRIVERS

115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000

FUNCTIONAL BLOCK DIAGRAM

Note that channels A and B are electrically isolated.

100

125

150

TEMPERATURE in

Dwg. GK-018-1

ALLOWABLE PACKAGE POWER DISSIPATION in WATTS

R = 5.0

C/W

R = 28

C/W

ALLOWABLE PACKAGE

POWER DISSIPATION

PROGRAMMABLE

PWM OFF TIMER

NOISE FILTER

D/A

LATCHES

SHIFT REG

GROUND

Dwg. FK-006

SENSE

CONTROL

SUPPLY

OUT

A/B

OUT

A/B

REF/ENABLE

CHANNEL A PIN NUMBERS

CHANNEL B PIN NUMBERS

V 1

PHASE

STROBE

DATA

CLOCK

ENABLE

REF

DC ELECTRICAL CHARACTERISTICS at T

= +25

C, V

= 5 V unless otherwise noted.

Limits

Characteristic

Symbol

Test Conditions

Min

Typ

Max

Units

FET Leakage Current

DSS

= 100 V

4.0

FET ON Voltage

DS(ON)

SLA7042M, I

OUT

= 1.2 A

800

SLA7044M, I

OUT

= 3 A

855

FET ON Resistance

DS(on)

SLA7042M, I

OUT

= 1.2 A

0.67

SLA7044M, I

OUT

= 3 A

0.285

Body Diode Forward Voltage

SLA7042M, I

OUT

= 1.2 A

1.2

SLA7044M, I

OUT

= 3 A

1.6

Control Supply Voltage

Operating

4.5

5.0

5.5

Control Supply Current

Each controller, V

= 5.5 V

7.0

Logic Input Voltage

IN(1)

3.5

IN(0)

1.5

Logic Input Current

IN(1)

= V

1.0

IN(0)

= 0

1.0

REF/ENABLE Input Voltage

REF/EN

DATA, CLOCK, STROBE, and OUT Enabled

0.4

2.5

DATA, CLOCK, STROBE, and OUT Disabled

- 1

REF/ENABLE Input Current

REF/EN

0 V

REF/EN

5 V

1.0

Step Reference

SRCR

DATA Input = 000X

Current Ratio

DATA Input = 001X

DATA Input = 010X

DATA Input = 011X

55.5

First Bit Entered (X) = Phase

DATA Input = 100X

71.4

Second Bit Entered = LSB

DATA Input = 101X

Last Bit Entered = MSB

DATA Input = 110X

DATA Input = 111X

100

NOTE: Negative current is defined as coming out of (sourcing) the specified device pin.

TYPICAL AC CHARACTERISTICS

= +25

C, V

= 5 V, I

OUT

= 1 A, Logic Levels are V

and

Ground

PWM OFF Time

DATA Input = 001X ................................................................. 7

DATA Input = 010X ................................................................. 7

DATA Input = 011X ................................................................. 9

DATA Input = 100X ................................................................. 9

DATA Input = 101X ................................................................. 9

DATA Input = 110X ................................................................ 11

DATA Input = 101X ................................................................ 11

Output RiseTime

10% to 90% ........................................................................... 0.5

Output Fall Time

90% to 10% ........................................................................... 0.1

Strobe-to-Output Switching Time

50% to 50% ........................................................................... 0.7

SLA7042M

AND

SLA7044M

MICROSTEPPING,
UNIPOLAR PWM, HIGH-CURRENT
MOTOR CONTROLLER/DRIVERS

SLA7042M

AND

SLA7044M

MICROSTEPPING,
UNIPOLAR PWM, HIGH-CURRENT
MOTOR CONTROLLER/DRIVERS

115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000

CLOCK

DATA

STROBE

Dwg. WK-002

SERIAL PORT TIMING CONDITIONS

= +25

C, Logic Levels are V

and Ground)

A. Minimum Data Active Time Before Clock Falling Edge (Data Set-Up Time) ........... 150 ns
B. Minimum Data Active Time After Clock Falling Edge (Data Hold Time) .................. 150 ns
C. Minimum Data Pulse Width ...................................................................................... 350 ns
D. Minimum Clock Pulse Width .................................................................................... 350 ns
E. Minimum Time Between Clock and Strobe Falling Edges ....................................... 650 ns
F. Minimum Strobe Pulse Width ................................................................................... 500 ns

APPLICATIONS INFORMATION

The SLA7042M and SLA7044M modules integrate two

CMOS controller ICs and four NMOS FETs. Each half of the
device operates independently, although the CLOCK inputs
may be connected together and the STROBE inputs may be
connected together. Pulling V

REF/EN

low (<2.5 V) allows the 4-

bit shift registers to be serially loaded with motor phase and
output currrent ratioing data.

The first bit selects the motor phase (logic high = Output A

or B, logic low = Output A or B); the next three bits determine
the motor current ratio (eight steps, 0% to 100%). The internal
D/A converter, in conjunction with a current-sensing resistor
and input reference voltage, completes the microstepping
current control.

Pulling V

REF/EN

high (within 1 V of V

) resets the shift

FIGURE 2. PWM CONTROL (RUN MODE)

Dwg. EK-011

V b

CONTROL

LOGIC

DRIVE

R 2

REF/EN

PWM

OFF-TIME

CONTROL

SENSE

SERIAL DATA

D/A

TO CHANNEL B

ENABLE

DATA

SERIAL DATA INPUT ENABLE

In a minimum-component application, a voltage divider

provides V

REF/EN

and an npn transistor provides the

required pull-down to enable the serial data input as
shown in Figure 2.

OUT

max

+ R

3 · R

P STEPPER MOTOR CONTROL

Alternative REFERENCE/ENABLE input configura-

tions provide for more complete motor control. A tri-state
logic element and a voltage divider allows a fixed refer-
ence voltage, with both output disable and data enable
functions. Complete

P control is usually accomplished

with a D/A converter as shown in Figure 3. Here, digital
control provides an output disable (>V

- 1 V), V

REF

, and

(<2.5 V).

SLA7042M

AND

SLA7044M

MICROSTEPPING,
UNIPOLAR PWM, HIGH-CURRENT
MOTOR CONTROLLER/DRIVERS

Dwg. WK-001

PHASE A

OUT

REGULATING THE PWM OUTPUT CURRENT

The output current (and motor coil current) waveform

is illustrated in Figure 1. Setting the maximum PWM
current trip point to meet the specified full-step running
current for the motor, I

OUT

max (DATA input = 111X =

100% ratio), requires only a current-sensing resistor, R

and an input reference voltage, V

REF/EN

, between 0.4 V

and 2.5 V.

OUT

max

REF/EN

3 · R

FIGURE 1. PHASE A COIL CURRENT WAVEFORM

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