5881
BiMOS II DUAL
8-BIT LATCHED DRIVER
DISCONTINUED PRODUCT
-- FOR REFERENCE ONL
Y
With 16 CMOS data latches (two sets of eight), CMOS control
circuitry for each set of latches, and a bipolar saturated driver for each
latch, the UCN5881EP provides low-power interface with maximum
flexibility. The driver includes thermal shutdown circuitry to protect
against damage from high junction temperatures and clamp diodes
for inductive load transient suppression.
The CMOS inputs cause minimal circuit loading and are compat-
ible with standard CMOS, PMOS, and NMOS circuits. TTL or DTL
circuits may require the use of appropriate pull up resistors. When
reading back, each data input will sink 8 mA (if its corresponding latch
is low) or source 400
A (if its corresponding latch is high). The read
back feature is for error checking. It allows the system to verify that
data has been received and latched.
The bipolar outputs are suitable for use with low-power relays,
solenoids, and stepping motors. The very-low output saturation
voltage makes this device well-suited for driving LED arrays. The
output transistors are capable of sinking 50 mA and will maintain at
least 20 V in the OFF state. Outputs may be paralleled for higher
current capability.
The UCN5881EP dual 8-bit latched sink driver is rated for opera-
tion over the temperature range of -20
C to +85
C and is supplied in a
plastic 44-lead chip carrier conforming to the JEDEC MS-007AB
outline.
FEATURES
s
4.4 MHz Minimum Data-Input Rate
s
Low-Power CMOS Logic
s
20 V, 50 mA (Max.) Outputs
s
Transient-Protected Outputs
s
Thermal Shutdown Protection
s
Low-Profile Leaded Chip Carrier
5881
BiMOS II DUAL 8-BIT LATCHED
DRIVER WITH READ BACK
Always order by complete part number:
UCN5881EP .
ABSOLUTE MAXIMUM RATINGS
Output Voltage, V
OUT
. . . . . . . . . . . . . . 20 V
Output Sustaining Voltage, V
CE(sus)
. . . 15 V
Output Current, I
OUT
. . . . . . . . . . . . 50 mA
Input Voltage Range,
V
IN
. . . . . . . . . . . -0.3 V to V
DD
+ 0.3 V
Logic Supply Voltage, V
DD
. . . . . . . . . . 15 V
Package Power Dissipation,
P
D
. . . . . . . . . . . . . . . . . . . See Graph
Operating Temperature Range,
T
A
. . . . . . . . . . . . . . . . -20
C to +85
C
Storage Temperature Range,
T
S
. . . . . . . . . . . . . . . -55
C to +150
C
Caution: CMOS devices have input static
protection, but are susceptible to damage when
exposed to extremely high static electrical
charges.
Dwg. No. A-14,225
Data Sheet
26180.16
5881
BiMOS II DUAL
8-BIT LATCHED DRIVER
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
FUNCTIONAL BLOCK DIAGRAM
(1 of 16 Channels)
Output
Latch
Read/ln Strobe Clear
Enable
Read/Write Contents
Output
X
X
X
1
X
X
OFF
0
1
0
0
1
0
OFF
1
1
0
0
1
1
ON
X
0
0
0
1
n-1
n-1
X
X
1
X
X
0
OFF
n
X
0
X
0
n
n
n = Present Latch Contents
n-1 = Previous Latch Contents
X = Irrelevant
50
75
100
125
150
2.5
0.5
0
ALLOWABLE PACKAGE POWER DISSIPATION IN WATTS
AMBIENT TEMPERATURE IN
C
2.0
1.5
1.0
25
Dwg. GP-025-1A
3.0
R = 46
C/W
JA
Dwg. No. A-14,227
W
Copyright 1985, 1995
,
Allegro MicroSystems, Inc.
TRUTH TABLE
5881
BiMOS II DUAL
8-BIT LATCHED DRIVER
Limits
Characteristic
Symbol
Test Conditions
Min.
Max.
Units
Output Leakage Current
I
CEX
V
OUT
= 20 V
--
50
A
Output Saturation Voltage
V
CE(SAT)
I
OUT
= 10 mA
--
0.1
V
I
OUT
= 25 mA
--
0.5
V
Output Sustaining Voltage
V
CE(sus)
I
OUT
= 25 mA, L = 2 mH
15
--
V
Input Voltage
V
IN(0)
-0.3
0.8
V
V
IN(1)
3.5
5.3
V
Input Current
I
IN(0)
V
IN
= 0.8 V
--
-10
A
I
IN(1)
V
IN
= 5 V
--
10
A
Readback Output Voltage
V
OUT(1)
I
OUT
= -400
A
3.5
--
V
V
OUT(0)
I
OUT
= 5.0 mA
--
0.8
V
Logic Supply Current
l
DD
All Drivers ON
--
14
mA
All Drivers OFF
--
3.0
mA
Clamp Diode Leakage Current
I
R
V
R
= 20 V
--
50
A
Clamp Diode Forward Voltage
V
F
I
F
= 50 mA
--
1.5
V
ELECTRICAL CHARACTERISTICS at T
A
= 25
C, V
DD
= 5 V (unless otherwise noted).
A high on the READ/WRITE input allows
the circuit to accept data in. Information then
present at an input is transferred to its latch
when the STROBE is high. A high CLEAR
input will set all latches to the output OFF
condition regardless of the data or STROBE
input levels. A high OUTPUT ENABLE will
set all outputs to the OFF condition regard-
less of any other input conditions. When the
OUTPUT ENABLE is low, the outputs de-
pend on the state of their respective latches.
A low on the READ/WRITE input will
allow the latched data to be read back on the
data input lines. Allow a minimum of 750 ns
delay (will increase with capacitive loading)
before reading back the state of the latches.
The read back feature is for error checking
applications and allows the system to verify
that data has been received and latched.
Dwg. No. A-14,228
TIMING CONDITIONS
(V
DD
= 5.0 V, Logic Levels are V
DD
and Ground)
A. Minimum Data Active Time Before Strobe Enabled
(Data Set-Up Time) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 ns
B. Minimum Data Active Time After Strobe Disabled
(Data Hold Time) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 ns
C. Minimum Strobe Pulse Width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 ns
D. Typical Time Between Strobe Activation and Output
ON to OFF Transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
s
E. Typical Time Between Strobe Activation and Output
OFF to ON Transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500 ns
F. Minimum Clear Pulse Width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 ns
G. Minimum Data Pulse Width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 ns
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