5895
8-BIT SERIAL-INPUT,
LATCHED DRIVERS
BiMOS II 8-BIT SERIAL INPUT,
LATCHED SOURCE DRIVERS
The UCN5895A, UCN5895EP, and A5895SLW BiMOS II serial-
input, latched source drivers are designed for applications emphasiz-
ing low output saturation voltages and currents to -250 mA per output.
These smart high-side octal, driver ICs merge an 8-bit CMOS shift
register, associated CMOS latches, and CMOS control logic (strobe
and output enable) with medium current emitter-follower (sourcing)
outputs. Typical applications include incandescent or LED displays
(both directly driven and multiplexed), non-impact (i.e., thermal)
printers, relays, and solenoids.
Each device is suitable for high-side applications to -250 mA per
channel. The maximum supply voltage is 50 V and a minimum output
sustaining voltage rating of 35 V for inductive load applications. Under
normal operating conditions, the UCN5895A and UCN5895EP are
capable of providing -120 mA (8 outputs continuous and simultaneous)
at +65
C with a logic supply of 5 V. Similar devices, with higher output
current ratings, are the UCN5890A and UCN5891A.
BiMOS II devices can operate at greatly improved data-input rates.
With a 5 V supply, they will typically operate at better than 5 MHz.
At 12 V, significantly higher speeds are obtained.
The CMOS inputs provide for minimum loading and are compatible
with standard CMOS, PMOS, and NMOS circuits. TTL or DTL circuits
may require the use of appropriate pull-up resistors to ensure a proper
input-logic high. A CMOS serial data output allows cascading these
devices in multiple drive-line applications required by many dot matrix,
alphanumeric, and bar graph displays.
These devices are rated for continuous operation over the tem-
perature range of -20
C to +85
C. Because of limitations on package
power dissipation, the simultaneous operation of all output drivers may
require a reduction in duty cycle. The UCN5895A is supplied in a
standard 16-pin dual in-line plastic package with a copper lead frame
for increased allowable package power dissipation. The UCN5895EP
is supplied in a 20-lead plastic leaded chip carrier for minimum area,
surface-mount applications. The A5895SLW is supplied in a 16-lead
wide-body plastic SOIC.
FEATURES
s
Low Output-Saturation Voltage
s
Source Outputs to 50 V
s
Output Current to -250 mA
s
To 3.3 MHz Data-lnput Rate
s
Low-Power CMOS Logic & Latches
Always order by complete part number, e.g.,
UCN5895A .
UCN5895A
Data Sheet
26182.14B*
Note the UCN5895A (DIP) and the A5895SLW
(SOIC) are electrically identical and share a common
terminal number assignment.
ABSOLUTE MAXIMUM RATINGS
at T
A
= +25
C
Output Voltage, V
OUT
. . . . . . . . . . . . . . 50 V
Logic Supply Voltage Range,
V
DD
. . . . . . . . . . . . . . . . . . 4.5 V to 12 V
Driver Supply Voltage Range,
V
BB
. . . . . . . . . . . . . . . . . . 5.0 V to 50 V
Input Voltage Range,
V
IN
. . . . . . . . . . . -0.3 V to V
DD
+ 0.3 V
Continuous Output Current,
I
OUT
. . . . . . . . . . . . . . . . . . . . . -250 mA
Allowable Package Power Dissipation,
P
D
. . . . . . . . . . . . . . . . . . . . See Graph
Operating Temperature Range,
T
A
. . . . . . . . . . . . . . . . . -20
C to +85
C
Storage Temperature Range,
T
S
. . . . . . . . . . . . . . . . -55
C to +150
C
Caution: CMOS devices have input-static
protection, but are susceptible to damage when
exposed to extremely high static electrical
charges.
5895
2
3
4
5
6
7
8
SERIAL
DATA OUT
SERIAL
DATA IN
OUTPUT
ENABLE
LOGIC
SUPPLY
STROBE
CLOCK
CLK
V
DD
ST
OE
1
GROUND
9
10
11
12
13
14
15
16
OUT
1
OUT
2
OUT
3
Dwg. PP-026-2A
OUT
5
OUT
6
OUT
7
OUT
8
OUT
4
SHIFT
REGISTER
LATCHES
V
BB
LOAD
SUPPLY
5895
8-BIT SERIAL-INPUT,
LATCHED DRIVERS
ELECTRICAL CHARACTERISTICS at T
A
= +25
C, V
BB
= 50 V, V
DD
= 5 V and 12 V
(unless otherwise noted).
Limits
Characteristic
Symbol
Test Conditions
Min.
Max.
Units
Output Leakage Current
I
OUT
T
A
= +25
C
--
-50
A
T
A
= +70
C
--
-100
A
Output Saturation Voltage
V
CE(SAT)
I
OUT
= -60 mA
--
1.1
V
I
OUT
= -120 mA
--
1.2
V
Output Sustaining Voltage
V
CE(sus)
I
OUT
= -120 mA, L = 2 mH
35
--
V
Input Voltage
V
IN(1)
V
DD
= 5.0 V
3.5
5.3
V
V
DD
= 12 V
10.5
12.3
V
V
IN(0)
V
DD
= 5 V to 12 V
-0.3
+0.8
V
Input Current
I
IN(1)
V
DD
= V
IN
= 5.0 V
--
50
A
V
DD
= V
IN
= 12 V
--
240
A
Input lmpedance
z
IN
V
DD
= 5.0 V
100
--
k
V
DD
= 12 V
50
--
k
Max. Clock Frequency
f
CLK
3.3
--
MHz
Serial Data-Output
r
OUT
V
DD
= 5.0 V
--
20
k
V
DD
= 12 V
--
6.0
k
Turn-ON Delay
t
PLH
Output Enable to Output, I
OUT
= -120 mA
--
2.0
s
Turn-OFF Delay
t
PHL
Output Enable to Output, I
OUT
= -120 mA
--
10
s
Supply Current
I
BB
All outputs ON, All outputs open
--
10
mA
All outputs OFF
--
200
A
I
DD
V
DD
= 5 V, All outputs OFF, Inputs = 0 V
--
100
A
V
DD
= 12 V, All outputs OFF, Inputs = 0 V
--
200
A
V
DD
= 5 V, One output ON, All inputs = 0 V
--
1.0
mA
V
DD
= 12 V, One output ON, All inputs = 0 V
--
3.0
mA
Diode Leakage Current
I
R
V
R
= 25 V, T
A
= +25
C
--
50
A
V
R
= 25 V, T
A
= +70
C
--
100
A
Diode Forward Voltage
V
F
I
F
= 120 mA
--
2.0
V
Resistance
5895
8-BIT SERIAL-INPUT,
LATCHED DRIVERS
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
TIMING CONDITIONS
(V
DD
= 5.0 V, Logic Levels are V
DD
and Ground)
A.
Minimum Data Active Time Before Clock Pulse
(Data Set-Up Time) ................................................................. 75 ns
B.
Minimum Data Active Time After Clock Pulse
(Data Hold Time) ..................................................................... 75 ns
C.
Minimum Data Pulse Width ........................................................ 150 ns
D.
Minimum Clock Pulse Width ...................................................... 150 ns
E.
Minimum Time Between Clock Activation and Strobe ............... 300 ns
F.
Minimum Strobe Pulse Width ..................................................... 100 ns
G.
Typical Time Between Strobe Activation and
Output Transition .................................................................... 1.0
s
Serial Data present at the input is transferred to the shift register
on the logic "0" to logic "1" transition of the CLOCK input pulse. On
succeeding CLOCK pulses, the registers shift data information towards
the SERIAL DATA OUTPUT. The SERIAL DATA must appear at the
input prior to the rising edge of the CLOCK input waveform.
Information present at any register is transferred to its respective
latch when the STROBE is high (serial-to-parallel conversion). The
latches will continue to accept new data as long as the STROBE is
held high. Applications where the latches are bypassed (STROBE tied
high) will require that the OUTPUT ENABLE input be high during serial
data entry.
When the OUTPUT ENABLE input is high, all of the output buffers
are disabled (OFF) without affecting the information stored in the
latches or shift register. With the OUTPUT ENABLE input low, the
outputs are controlled by the state of their respective latches.
Dwg. No. A-12,649A
E F
CLOCK
DATA IN
STROBE
BLANKING
OUT
N
A D
B
C
G
PDF 
ZIP
