DISCONTINUED PRODUCT
-- FOR REFERENCE ONL
Y
Recommended replacement --
A6812
2
3
4
5
6
7
8
9
12
13
14
15
16
28
1
V
DD
Dwg. PP-059-1
OUT
10
OUT
20
OUT
11
OUT
19
REGISTER
LATCHES
V
BB
CLOCK
ST
CLK
26
27
22
23
24
25
SERIAL
DATA OUT
LOAD
SUPPLY
SERIAL
DATA IN
10
11
STROBE
GROUND
LOGIC
SUPPLY
19
20
21
BLANKING
17
18
OUT
9
OUT
1
OUT
2
OUT
8
OUT
18
OUT
12
LATCHES
REGISTER
BiMOS II 20-BIT SERIAL-INPUT, LATCHED
SOURCE DRIVERS FOR -40
C TO +85
C OPERATION
The UCQ5812AF/EPF combine a 20-bit CMOS shift register, data
latches, and control circuitry with high-voltage bipolar source drivers and
active DMOS pull-downs for reduced supply current requirements. Although
designed primarily for vacuum-fluorescent displays, the high-voltage, high-
current outputs also allow them to be used in other peripheral power driver
applications.
The CMOS shift register and latches allow direct interfacing with
microprocessor-based systems. With a 5 V supply, they will operate to at
least 3.3 MHz. At 12 V, higher speeds are possible. Especially useful for
inter-digit blanking, the BLANKING input disables the output source drives
and turns on the DMOS sink drivers. Use with TTL may require the use of
appropriate pull-up resistors to ensure an input logic high.
A CMOS serial data output enables cascade connections in applications
requiring additional drive lines. Similar devices are available as the
UCQ5810AF/LWF (10 bits), UCQ5811A (12 bits), and UCQ5818AF/EPF
(32 bits).
The output source drivers are high-voltage PNP-NPN Darlingtons with a
minimum breakdown of 60 V and are capable of sourcing up to 40 mA. The
DMOS active pull-downs are capable of sinking up to 15 mA.
The UCQ5812AF is supplied in a 28-pin dual in-line plastic package with
0.600" (15.24 mm) row spacing. For surface mounting, the UCQ5812EPF is
furnished in 28-lead plastic chip carrier (quad pack) with 0.050"(1.22 mm)
centers. Copper lead-frames, reduced supply current requirements and lower
output saturation voltages, allow continuous operation, with all outputs
sourcing 25 mA, of the UCQ5812AF over the operating temperature range,
and the UCQ5812EPF up to +75
C.
Always order by complete part number, e.g.,
UCQ5812AF .
FEATURES
s
High-Speed Source Drivers
s
60 V Source Outputs
s
To 3.3 MHz Data Input Rate
s
Low-Output Saturation Voltages
s
Low-Power CMOS Logic and Latches
s
Active DMOS Pull-Downs
s
Reduced Supply Current
Requirements
s
Improved Replacement
for TL5812
Data Sheet
26182.27B
UCQ5812EPF
ABSOLUTE MAXIMUM RATINGS
at T
A
= 25
C
Logic Supply Voltage, V
DD
..................... 15 V
Driver Supply Voltage, V
BB
.................... 60 V
Continuous Output Current Range,
I
OUT
................................. -40 to +15 mA
Input Voltage Range,
V
IN
........................ -0.3 V to V
DD
+ 0.3 V
Package Power Dissipation, P
D
(UCQ5812AF) ........................... 3.12 W*
(UCQ5812EPF) ........................ 1.84 W
Operating Temperature Range,
T
A
.................................. -40
C to +85
C
Storage Temperature Range,
T
S
................................ -55
C to +150
C
* Derate at rate of 22 mW/
C above T
A
= +25
C
Derate at rate of 15 mW/
C above T
A
= +25
C
Caution: Allegro CMOS devices have input static
protection but are susceptible to damage when
exposed to extremely high static electrical
charges.
Note that the UCQ5812AF (dual in-line package)
and UCQ5812EPF (PLCC package) are
electrically identical and share a common pin
number assignment.
5812-F
5812-F
20-BIT SERIAL-INPUT,
LATCHED SOURCE DRIVERS
FOR -40
C TO +85
C OPERATION
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
UCQ5812AF
FUNCTIONAL BLOCK DIAGRAM
TYPICAL INPUT CIRCUIT
TYPICAL OUTPUT DRIVER
V
OUT
BB
N
Dwg. No. A-14,219
4
5
6
7
8
9
10
19
20
21
22
23
24
25
LOAD
SUPPLY
BB
V
OUT
2
OUT
7
OUT
8
Dwg. PP-029-7
OUT
19
OUT
18
OUT
13
12
13
14
27
28
17
18
SERIAL
DATA OUT
BLANKING
LOGIC
SUPPLY
STROBE
GROUND
CLOCK
CLK
ST
BLNK
OUT
9
OUT
10
OUT
12
OUT
11
11
LATCHES
REGISTER
REGISTER
LATCHES
2
3
26
27
28
SERIAL
DATA IN
OUT
6
OUT
1
OUT
4
OUT
3
OUT
20
1
15
16
OUT
5
OUT
17
OUT
16
OUT
15
OUT
14
DD
V
Dwg. EP-010-5
IN
V
DD
Copyright 1995, 2002 Allegro MicroSystems, Inc.
MOS
BIPOLAR
OUT
1
OUT
2
GROUND
Dwg. FP-013-1
OUT
3
OUT
N
CLOCK
SERIAL
DATA IN
STROBE
BLANKING
SERIAL
DATA OUT
SERIAL-PARALLEL SHIFT REGISTER
LATCHES
V
DD
V
BB
LOGIC
SUPPLY
LOAD
SUPPLY
5812-F
20-BIT SERIAL-INPUT,
LATCHED SOURCE DRIVERS
FOR -40
C TO +85
C OPERATION
www.allegromicro.com
ELECTRICAL CHARACTERISTICS over operating temperature range, at V
BB
= 60 V (unless
otherwise noted).
Limits @ V
DD
= 5 V
Limits @ V
DD
= 12 V
Characteristic
Symbol
Test Conditions
Mln.
Typ.
Max.
Min.
Typ.
Max.
Units
Output Leakage Current
I
CEX
V
OUT
= 0 V, T
A
= +70
C
--
-5.0
-15
--
-5.0
-15
A
Output Voltage
V
OUT(1)
I
OUT
= -25 mA, V
BB
= 60 V
58
58.5
--
58
58.5
--
V
V
OUT(0)
I
OUT
= 1 mA
--
2.0
3.0
--
--
--
V
I
OUT
= 2 mA
--
--
--
--
2.0
3.5
V
Output Pull-Down Current
I
OUT(0)
V
OUT
= 5 V to V
BB
2.0
3.5
--
--
--
--
mA
V
OUT
= 20 V to V
BB
--
--
--
8.0
13
--
mA
Input Voltage
V
IN(1)
3.5
--
5.3
10.5
--
12.3
V
V
IN(0)
-0.3
--
+0.8
-0.3
--
+0.8
V
Input Current
I
IN(1)
V
IN
= V
DD
--
0.05
0.5
--
0.1
1.0
A
I
IN(0)
V
IN
= 0.8 V
--
-0.05
-0.5
--
-0.1
-1.0
A
Serial Data
V
OUT(1)
I
OUT
= -200
A
4.5
4.7
--
11.7
11.8
--
V
V
OUT(0)
I
OUT
= 200
A
--
200
250
--
100
200
mV
Maximum Clock Frequency
f
clk
3.3*
--
--
--
--
--
MHz
Supply Current
I
DD(1)
All Outputs High
--
100
300
--
200
500
A
I
DD(0)
All Outputs Low
--
100
300
--
200
500
A
I
BB(1)
Outputs High, No Load
--
1.5
4.0
--
1.5
4.0
mA
I
BB(0)
Outputs Low
--
10
100
--
10
100
A
Blanking to Output Delay
t
PHL
C
L
= 30 pF, 50% to 50%
--
2000
--
--
1000
--
ns
t
PLH
C
L
= 30 pF, 50% to 50%
--
1000
--
--
850
--
ns
Output Fall Time
t
f
C
L
= 30 pF, 90% to 10%
--
1450
--
--
650
--
ns
Output Rise Time
t
r
C
L
= 30 pF, 10% to 90%
--
650
--
--
700
--
ns
Negative current is defined as coming out of (sourcing) the specified device pin.
* Operation at a clock frequency greater than the specified minimum value is possible but not warranteed.
5812-F
20-BIT SERIAL-INPUT,
LATCHED SOURCE DRIVERS
FOR -40
C TO +85
C OPERATION
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
TRUTH TABLE
Serial
Shift Register Contents
Serial
Latch Contents
Output Contents
Data
Clock
Data
Strobe
Input
Input
I
1
I
2
I
3
...
I
N-1
I
N
Output
Input
I
1
I
2
I
3
...
I
N-1
I
N
Blanking
I
1
I
2
I
3
...
I
N-1
I
N
H
H
R
1
R
2
...
R
N-2
R
N-1
R
N-1
L
L
R
1
R
2
...
R
N-2
R
N-1
R
N-1
X
R
1
R
2
R
3
...
R
N-1
R
N
R
N
X
X
X
...
X
X
X
L
R
1
R
2
R
3
...
R
N-1
R
N
P
1
P
2
P
3
...
P
N-1
P
N
P
N
H
P
1
P
2
P
3
...
P
N-1
P
N
L
P
1
P
2
P
3
...
P
N1
P
N
X
X
X
...
X
X
H
L
L
L
...
L
L
L = Low Logic Level
H = High Logic Level
X = Irrelevant
P = Present State
R = Previous State
Dwg. No. 12,649A
TIMING REQUIREMENTS
(T
A
= +25
C,V
DD
= 5 V, Logic Levels are V
DD
and Ground)
A. Minimum Data Active Time Before Clock Pulse
(Data Set-Up Time) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 ns
B. Minimum Data Active Time After Clock Pulse
(Data Hold Time) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 ns
C. Minimum Data Pulse Width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 ns
D. Minimum Clock Pulse Width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 ns
E. Minimum Time Between Clock Activation and Strobe . . . . . . . . . . . 300 ns
F. Minimum Strobe Pulse Width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 ns
G. Typical Time Between Strobe Activation and
Output Transistion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500 ns
Timing is representative of a 3.3 MHz clock. Higher speeds may be attainable
with increased supply voltage; operation at high temperatures will reduce the
specified maximum clock frequency.
Serial Data present at the input is transferred
to the shift register on the logic "0" to logic "1"
transition of the CLOCK input pulse. On succeed-
ing CLOCK pulses, the registers shift data
information towards the SERIAL DATA OUT-
PUT. The SERIAL DATA must appear at the
input prior to the rising edge of the CLOCK input
waveform.
Information present at any register is trans-
ferred to the respective latch when the STROBE
is high (serial-to-parallel conversion). The latches
will continue to accept
new data as long as the STROBE is held high.
Applications where the latches are bypassed
(STROBE tied high) will require that the
BLANKING input be high during serial data
entry.
When the BLANKING input is high, the
output source drivers are disabled (OFF); the
DMOS sink drivers are ON, the information
stored in the latches is not affected by the
BLANKING input. With the BLANKING input
low, the outputs are controlled by the state of
their respective latches.
E F
CLOCK
DATA IN
STROBE
BLANKING
OUT
N
A D
B
C
G
5812-F
20-BIT SERIAL-INPUT,
LATCHED SOURCE DRIVERS
FOR -40
C TO +85
C OPERATION
www.allegromicro.com
UCQ5812AF
Dimensions in Inches
(controlling dimensions)
NOTES: 1. Exact body and lead configuration at vendor's option within limits shown.
2. Lead spacing tolerance is non-cumulative.
3. Lead thickness is measured at seating plane or below.
4. Supplied in standard sticks/tubes of 12 devices.
Dimensions in Millimeters
(for reference only)
28
14.73
12.32
1
2
3
6.35
MAX
1.77
0.77
0.39
MIN
0.558
0.356
0.381
0.204
15.24
BSC
Dwg. MA-003-28 mm
14
2.54
BSC
0.13
MIN
5.08
2.93
4
17.78
MAX
15
39.7
35.1
28
1
2
3
0.250
MAX
0.070
0.030
0.015
MIN
0.022
0.014
0.015
0.008
0.600
BSC
Dwg. MA-003-28 in
14
0.100
BSC
0.005
MIN
0.200
0.115
4
0.700
MAX
15
1.565
1.380
0.580
0.485
5812-F
20-BIT SERIAL-INPUT,
LATCHED SOURCE DRIVERS
FOR -40
C TO +85
C OPERATION
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
UCN5812EPF
Dimensions in Inches
(controlling dimensions)
NOTES: 1. Exact body and lead configuration at vendor's option within limits shown.
2. Lead spacing tolerance is non-cumulative.
3. Supplied in standard sticks/tubes of 38 devices or add "TR" to part number for tape and reel.
0.51
MIN
4.57
4.20
1.27
BSC
12.57
12.32
11.582
11.430
1
28
INDEX AREA
Dwg. MA-005-28A mm
0.812
0.661
0.331
0.533
12.57
12.32
26
25
19
18
12
11
4
5
11.58
11.43
5.56
4.85
5.56
4.85
18
12
0.020
MIN
0.050
BSC
1
28
INDEX AREA
Dwg. MA-005-28A in
0.026
0.032
0.013
0.021
26
25
19
11
4
5
0.165
0.180
0.495
0.485
0.456
0.450
0.495
0.485
0.456
0.450
0.219
0.191
0.219
0.191
Dimensions in Millimeters
(for reference only)
5812-F
20-BIT SERIAL-INPUT,
LATCHED SOURCE DRIVERS
FOR -40
C TO +85
C OPERATION
www.allegromicro.com
The products described here are manufactured under one or more
U.S. patents or U.S. patents pending.
Allegro MicroSystems, Inc. reserves the right to make, from time to
time, such departures from the detail specifications as may be
required to permit improvements in the performance, reliability, or
manufacturability of its products. Before placing an order, the user is
cautioned to verify that the information being relied upon is current.
Allegro products are not authorized for use as critical components
in life-support devices or systems without express written approval.
The information included herein is believed to be accurate and
reliable. However, Allegro MicroSystems, Inc. assumes no responsi-
bility for its use; nor for any infringement of patents or other rights of
third parties which may result from its use.
5812-F
20-BIT SERIAL-INPUT,
LATCHED SOURCE DRIVERS
FOR -40
C TO +85
C OPERATION
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
POWER
INTERFACE DRIVERS
Function
Output Ratings*
Part Number
SERIAL-INPUT LATCHED DRIVERS
8-Bit (saturated drivers)
-120 mA
50 V
5895
8-Bit
350 mA
50 V
5821
8-Bit
350 mA
80 V
5822
8-Bit
350 mA
50 V
5841
8-Bit
350 mA
80 V
5842
8-Bit (constant-current LED driver)
75 mA
17 V
6275
8-Bit (constant-current LED driver)
120 mA
24 V
6277
8-Bit (DMOS drivers)
250 mA
50 V
6595
8-Bit (DMOS drivers)
350 mA
50 V
6A595
8-Bit (DMOS drivers)
100 mA
50 V
6B595
10-Bit (active pull-downs)
-25 mA
60 V
5810-F and 6810
12-Bit (active pull-downs)
-25 mA
60 V
5811
16-Bit (constant-current LED driver)
75 mA
17 V
6276
20-Bit (active pull-downs)
-25 mA
60 V
5812-F and 6812
32-Bit (active pull-downs)
-25 mA
60 V
5818-F and 6818
32-Bit
100 mA
30 V
5833
32-Bit (saturated drivers)
100 mA
40 V
5832
PARALLEL-INPUT LATCHED DRIVERS
4-Bit
350 mA
50 V
5800
8-Bit
-25 mA
60 V
5815
8-Bit
350 mA
50 V
5801
8-Bit (DMOS drivers)
100 mA
50 V
6B273
8-Bit (DMOS drivers)
250 mA
50 V
6273
SPECIAL-PURPOSE DEVICES
Unipolar Stepper Motor Translator/Driver
1.25 A
50 V
5804
Addressable 8-Bit Decoder/DMOS Driver
250 mA
50 V
6259
Addressable 8-Bit Decoder/DMOS Driver
350 mA
50 V
6A259
Addressable 8-Bit Decoder/DMOS Driver
100 mA
50 V
6B259
Addressable 28-Line Decoder/Driver
450 mA
30 V
6817
*
Current is maximum specified test condition, voltage is maximum rating. See specification for sustaining voltage limits.
Negative current is defined as coming out of (sourcing) the output.
Complete part number includes additional characters to indicate operating temperature range and package style.
Internal transient-suppression diodes included for inductive-load protection.
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