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Organization: 2M8 / 1M16
Sector architecture
- One 16K; two 8K; one 32K; and thirty-one 64K byte sectors
- One 8K; two 4K; one 16K; and thirty-one 32K word sectors
- Boot code sector architecture--T (top) or B (bottom)
- Erase any combination of sectors or full chip
Single 2.7-3.6V power supply for read/write operations
Sector protection
High speed 70/80/90/120 ns address access time
Automated on-chip programming algorithm
- Automatically programs/verifies data at specified address
Automated on-chip erase algorithm
- Automatically preprograms/erases chip or specified
sectors
Hardware RESET pin
- Resets internal state machine to read mode
Low power consumption
- 200 nA typical automatic sleep mode current
- 200 nA typical standby current
- 10 mA typical read current
JEDEC standard software, packages and pinouts
- 48-pin TSOP
- 44-pin SO (availability TBD)
CFI (Common Flash Interface) compliant
Detection of program/erase cycle completion
- DQ7 DATA polling
- DQ6 toggle bit
- RY/BY output
Erase suspend/resume
- Supports reading data from or programming data to a
sector not being erased
Low V
CC
write lock-out below 1.5V
10 year data retention at 150C
100,000 write/erase cycle endurance
/RJLF EORFN GLDJUDP
X decoder
V
CC
V
SS
Cell matrix
Y decoder
Y gating
Data latch
Chip enable
A
d
dr
es
s
la
t
c
h
Input/output
buffers
Sector protect/
Command
register
Program/erase
control
V
CC
detector
Erase voltage
generator
Program voltage
generator
Timer
A0A19
CE
OE
STB
STB
Output enable
Logic
RY/BY
WE
RESET
DQ0DQ15 (A-1)
switches
erase voltage
BYTE
6HOHFWLRQ JXLGH
29LV160-70
29LV160-80
29LV160-90
29LV160-120
Unit
Maximum access time
t
AA
70
80
90
120
ns
Maximum chip enable access time
t
CE
70
80
90
120
ns
Maximum output enable access time
t
OE
30
30
35
50
ns
3LQ DUUDQJHPHQW
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
A14
A15
A16
BYTE
V
SS
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
V
CC
A6
A5
A4
A3
A2
A1
A0
CE
V
SS
OE
DQ0
DQ8
DQ1
DQ9
DQ2
DQ10
44-pin SO
21
22
DQ3
DQ11
A10
A11
A12
A13
2
A18
3
A17
4
A7
1
Reset
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
43
42
41
44
A19
A8
A9
WE
A8 A9
A10 A11 A12 A13 A14 A15
A
1
6
BY
T
E
V
SS
D
Q
15/
A-
1
DQ7
DQ1
4
A19
NC
WE
RE
S
E
T
NC
NC
RY
/
B
Y
A18
D
Q
2
DQ1
0
DQ3 DQ1
1
V
CC
DQ4 DQ1
2
DQ5
DQ6
DQ1
3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
48
47
46
45
44
43
42
41
40
39
38
37
36
35
15
16
34
33
48-pin TSOP
A17
A7
A6
A5
A4
A3
A2
A1
A
0
CE
V
SS
OE
DQ0 DQ8 DQ1 DQ9
17
18
19
20
21
22
32
31
30
29
28
27
23
24
26
25
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P. 2 of 29
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The AS29LV160 is a 16 megabit, 3.0 volt Flash memory organized as 2 Megabyte of 8 bits/1 Megabyte of 16 bits each. For
flexible erase and program capability, the 8 megabits of data is divided into thirty-five sectors: one 16K, two 8K, one 32K, and
thirty-one 64k byte sectors; or one 8K, two 4K, one 16K, and thirty-one 32K word sectors. The 8 data appears on DQ0DQ7;
the 16 data appears on DQ0DQ15. The AS29LV160 is offered in JEDEC standard 48-pin TSOP, 48-pin BGA, and 44-pin SO
(availability TBD) packages. This device is designed to be programmed and erased in-system with a single 3.0V V
CC
supply. The
device can also be reprogrammed in standard EPROM programmers.
The AS29LV160 offers access times of 70/80/90/120 ns, allowing 0-wait state operation of high speed microprocessors. To
eliminate bus contention the device has separate chip enable (CE), write enable (WE), and output enable (OE) controls. Word
mode (16 output) is selected by BYTE = high. Byte mode (8 output) is selected by BYTE = low.
The AS29LV160 is fully compatible with the JEDEC single power supply Flash standard. Write commands are sent to the
command register using standard microprocessor write timings. An internal state-machine uses register contents to control the
erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase
operations. Read data from the device occurs in the same manner as other Flash or EPROM devices. Use the program command
sequence to invoke the automated on-chip programming algorithm that automatically times the program pulse widths and
verifies proper cell margin. Use the erase command sequence to invoke the automated on-chip erase algorithm that preprograms
the sector (if it is not already programmed before executing the erase operation), times the erase pulse widths, and verifies
proper cell margin.
Boot sector architecture enables the system to boot from either the top (AS29LV160T) or the bottom (AS29LV160B) sector.
Sector erase architecture allows specified sectors of memory to be erased and reprogrammed without altering data in other
sectors. A sector typically erases and verifies within 1.0 seconds. Hardware sector protection disables both program and erase
operations in all, or any combination of, the nineteen sectors. The device provides true background erase with Erase Suspend,
which puts erase operations on hold to either read data from, or program data to, a sector that is not being erased. The chip erase
command will automatically erase all unprotected sectors.
A factory shipped AS29LV160 is fully erased (all bits = 1). The programming operation sets bits to 0. Data is programmed into
the array one byte at a time in any sequence and across sector boundaries. A sector must be erased to change bits from 0 to 1.
Erase returns all bytes in a sector to the erased state (all bits = 1). Each sector is erased individually with no effect on other
sectors.
The device features single 3.0V power supply operation for Read, Write, and Erase functions. Internally generated and regulated
voltages are provided for the Program and Erase operations. A low V
CC
detector automatically inhibits write operations during
power transtitions. The RY/BY pin, DATA polling of DQ7, or toggle bit (DQ6) may be used to detect end of program or erase
operations. The device automatically resets to the read mode after program/erase operations are completed. DQ2 indicates which
sectors are being erased.
The AS29LV160 resists accidental erasure or spurious programming signals resulting from power transitions. Control register
architecture permits alteration of memory contents only after successful completion of specific command sequences. During
power up, the device is set to read mode with all program/erase commands disabled when V
CC
is less than V
LKO
(lockout
voltage). The command registers are not affected by noise pulses of less than 5 ns on OE, CE, or WE. To initiate write commands,
CE and WE must be logical zero and OE a logical 1.
When the device's hardware RESET pin is driven low, any program/erase operation in progress is terminated and the internal
state machine is reset to read mode. If the RESET pin is tied to the system reset circuitry and a system reset occurs during an
automated on-chip program/erase algorithm, data in address locations being operated on may become corrupted and requires
rewriting. Resetting the device enables the system's microprocessor to read boot-up firmware from the Flash memory.
The AS29LV160 uses Fowler-Nordheim tunnelling to electrically erase all bits within a sector simultaneously. Bytes are
programmed one at a time using EPROM programming mechanism of hot electron injection.
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2SHUDWLQJ PRGHV
L = Low (<V
IL
) = logic 0; H = High (>V
IH
) = logic 1; V
ID
= 10.0 1.0V; X = don't care.
In 16 mode, BYTE = V
IH
. In 8 mode, BYTE = V
IL
with DQ8-DQ14 in high Z and DQ15 = A-1.
Verification of sector protect/unprotect during A9 = V
ID.
0RGH GHILQLWLRQV
Mode
CE
OE
WE
A0
A1
A6
A9
RESET
DQ
ID read MFR code
L
L
H
L
L
L
V
ID
H
Code
ID read device code
L
L
H
H
L
L
V
ID
H
Code
Read
L
L
H
A0
A1
A6
A9
H
D
OUT
Standby
H
X
X
X
X
X
X
H
High Z
Output disable
L
H
H
X
X
X
X
H
High Z
Write
L
H
L
A0
A1
A6
A9
H
D
IN
Enable sector protect
L
V
ID
Pulse/L
L
H
L
V
ID
H
X
Sector unprotect
L
V
ID
Pulse/L
L
H
H
V
ID
H
X
Temporary sector
unprotect
X
X
X
X
X
X
X
V
ID
X
Verify sector protect
L
L
H
L
H
L
V
ID
H
Code
Verify sector unprotect
L
L
H
L
H
H
V
ID
H
Code
Hardware Reset
X
X
X
X
X
X
X
L
High Z
Item
Description
ID MFR code,
device code
Selected by A9 = V
ID
(9.5V10.5V), CE = OE = A1 = A6 = L, enabling outputs.
When A0 is low (V
IL
) the output data = 52h, a unique Mfr. code for Alliance Semiconductor Flash products.
When A0 is high (V
IH
), D
OUT
represents the device code for the AS29LV160.
Read mode
Selected with CE = OE = L, WE = H. Data is valid in t
ACC
time after addresses are stable, t
CE
after CE is low
and t
OE
after OE is low.
Standby
Selected with CE = H. Part is powered down, and I
CC
reduced to <1.0 A when CE = V
CC
0.3V = RESET. If
activated during an automated on-chip algorithm, the device completes the operation before entering
standby.
Output disable
Part remains powered up; but outputs tri-stated with OE pulled high.
Write
Selected with CE = WE = L, OE = H. Accomplish all Flash erasure and programming through the command
register. Contents of command register serve as inputs to the internal state machine. Address latching occurs
on the falling edge of WE or CE, whichever occurs later. Data latching occurs on the rising edge WE or CE,
whichever occurs first. Filters on WE prevent spurious noise events from appearing as write commands.
Enable
sector protect
Hardware protection circuitry implemented with external programming equipment causes the device to
disable program and erase operations for specified sectors. For in-system sector protection, refer to Sector
protect algorithm on page 15.
Sector unprotect
Disables sector protection for all sectors using external programming equipment. All sectors must be
protected prior to sector unprotection. For in-system sector unprotection, refer to Sector unprotect
algorithm on page 15.
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)OH[LEOH 6HFWRU $UFKLWHFWXUH
Verify sector
protect/
unprotect
Verifies write protection for sector. Sectors are protected from program/erase operations on commercial
programming equipment. Determine if sector protection exists in a system by writing the ID read command
sequence and reading location XXX02h, where address bits A1218 select the defined sector addresses. A
logical 1 on DQ0 indicates a protected sector; a logical 0 indicates an unprotected sector.
Temporary
sector unprotect
Temporarily disables sector protection for in-system data changes to protected sectors. Apply +10V to RESET
to activate temporary sector unprotect mode. During temporary sector unprotect mode, program protected
sectors by selecting the appropriate sector address. All protected sectors revert to protected state on removal
of +10V from RESET.
RESET
Resets the interal state machine to read mode. If device is programming or erasing when RESET = L, data
may be corrupted.
Deep
power down
Hold RESET low to enter deep power down mode (
<
1 A). Recovery time to start of first read cycle is 50ns.
Automatic sleep
mode
Enabled automatically when addresses remain stable for 300ns. Typical current draw is 1 A with no current
drawn by the external devices from teh output pin. Existing data is available to the system during this mode.
If an address is changed, automatic sleep mode is disabled and new data is returned within standard access
times.
Sector
Bottom boot sector architecture (AS29LV160B)
Top boot sector architecture (AS29LV160T)
8
16
Size
(Kbytes)
8
16
Size
(Kbytes)
0
000000-003FFF
00000-01FFF
16
000000-00FFFF
00000-07FFF
64
1
004000-005FFF
02000-02FFF
8
010000-01FFFF
08000-0FFFF
64
2
006000-007FFF
03000-03FFF
8
020000-02FFFF
10000-17FFF
64
3
008000-00FFFF
04000-07FFF
32
030000-03FFFF
18000-1FFFF
64
4
010000-01FFFF
08000-0FFFF
64
040000-04FFFF
20000-27FFF
64
5
020000-02FFFF
10000-17FFF
64
050000-05FFFF
28000-2FFFF
64
6
030000-03FFFF
18000-1FFFF
64
060000-06FFFF
30000-37FFF
64
7
040000-04FFFF
20000-27FFF
64
070000-07FFFF
38000-3FFFF
64
8
050000-05FFFF
28000-2FFFF
64
080000-08FFFF
40000-47FFF
64
9
060000-06FFFF
30000-37FFF
64
090000-09FFFF
48000-4FFFF
64
10
070000-07FFFF
38000-3FFFF
64
0A0000-0AFFFF
50000-57FFF
64
11
080000-08FFFF
40000-47FFF
64
0B0000-0BFFFF
58000-5FFFF
64
12
090000-09FFFF
48000-4FFFF
64
0C0000-0CFFFF
60000-67FFF
64
13
0A0000-0AFFFF
50000-57FFF
64
0D0000-0DFFFF
68000-6FFFF
64
14
0B0000-0BFFFF
58000-5FFFF
64
0E0000-0EFFFF
70000-77FFF
64
15
0C0000-0CFFFF
60000-67FFF
64
0F0000-0FFFFF
78000-7FFFF
64
16
0D0000-0DFFFF
68000-6FFFF
64
100000-10FFFF
80000-87FFF
64
17
0E0000-0EFFFF
70000-77FFF
64
110000-11FFFF
88000-8FFFF
64
18
0F0000-0FFFFF
78000-7FFFF
64
120000-12FFFF
90000-97FFF
64
Item
Description
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P. 5 of 29
In word mode, there are one 8K word, two 4K word, one 16K word, and fifteen 32K word sectors. Address range is A19A-1 if BYTE = V
IL
; address range is
A19A0 if BYTE = V
IH
.
,' 6HFWRU DGGUHVV WDEOH
19
100000-10FFFF
80000-87FFF
64
130000-13FFFF
98000-9FFFF
64
20
110000-11FFFF
88000-8FFFF
64
140000-14FFFF
A0000-A7FFF
64
21
120000-12FFFF
90000-97FFF
64
150000-15FFFF
A8000-AFFFF
64
22
130000-13FFFF
98000-9FFFF
64
160000-16FFFF
B0000-B7FFF
64
23
140000-14FFFF
A0000-A7FFF
64
170000-17FFFF
B8000-BFFFF
64
24
150000-15FFFF
A8000-AFFFF
64
180000-18FFFF
C0000-C7FFF
64
25
160000-16FFFF
B0000-B7FFF
64
190000-19FFFF
C8000-CFFFF
64
26
170000-17FFFF
B8000-BFFFF
64
1A0000-1AFFFF
D0000-D7FFF
64
27
180000-18FFFF
C0000-C7FFF
64
1B0000-1BFFFF
D8000-DFFFF
64
28
190000-19FFFF
C8000-CFFFF
64
1C0000-1CFFFF
E0000-E7FFF
64
29
1A0000-1AFFFF
D0000-D7FFF
64
1D0000-1DFFFF
E8000-EFFFF
64
30
1B0000-1BFFFF
D8000-DFFFF
64
1E0000-1EFFFF
F0000-F7FFF
64
31
1C0000-1CFFFF
E0000-E7FFF
64
1F0000-1F7FFF
F8000-FBFFF
32
32
1D0000-1DFFFF
E8000-EFFFF
64
1F8000-1F9FFF
FC000-FCFFF
8
33
1E0000-1EFFFF
F0000-F7FFF
64
1FA000-1FBFFF
FD000-FDFFF
8
34
1F0000-1FFFFF
F8000-FFFFF
64
1FC000-1FFFFF
FE000-FFFFF
16
Sector
Bottom boot sector architecture
(AS29LV160B)
Top boot sector architecture
(AS29LV160T)
A19
A18 A17 A16
A15
A14
A13
A12
A19
A18
A17
A16
A15
A14
A13
A12
0
0
0
0
0
0
0
0
X
0
0
0
0
0
X
X
X
1
0
0
0
0
0
0
1
0
0
0
0
0
1
X
X
X
2
0
0
0
0
0
0
1
1
0
0
0
1
0
X
X
X
3
0
0
0
0
0
1
X
X
0
0
0
1
1
X
X
X
4
0
0
0
0
1
X
X
X
0
0
1
0
0
X
X
X
5
0
0
0
1
0
X
X
X
0
0
1
0
1
X
X
X
6
0
0
0
1
1
X
X
X
0
0
1
1
0
X
X
X
7
0
0
1
0
0
X
X
X
0
0
1
1
1
X
X
X
8
0
0
1
0
1
X
X
X
0
1
0
0
0
X
X
X
9
0
0
1
1
0
X
X
X
0
1
0
0
1
X
X
X
10
0
0
1
1
1
X
X
X
0
1
0
1
0
X
X
X
11
0
1
0
0
0
X
X
X
0
1
0
1
1
X
X
X
Sector
Bottom boot sector architecture (AS29LV160B)
Top boot sector architecture (AS29LV160T)
8
16
Size
(Kbytes)
8
16
Size
(Kbytes)
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