Copyright Alliance Semiconductor. All rights reserved.
AS4LC256K16EO
2/25/02; V.1.2
Alliance Semiconductor
P. 1 of 24
3.3V 256K X 16 CMOS DRAM (EDO)
Features
Organization: 262,144 words 16 bits
High speed
- 45/50/60 ns RAS access time
- 10/12/15/20 ns column address access time
- 7/10/10 ns CAS access time
Low power consumption
- Active: 280 mW max (AS4LC256K16EO-45)
- Standby: 2.8 mW max, CMOS I/O (AS4LC256K16EO-45)
EDO page mode
5V I/O tolerant
512 refresh cycles, 8 ms refresh interval
- RAS-only or CAS-before-RAS refresh or self refresh
Read-modify-write
LVTTL-compatible, three-state I/O
JEDEC standard packages
- 400 mil, 40-pin SOJ
- 400 mil, 40/44-pin TSOP 2
3.3V power supply
Latch-up current > 200 mA
Pin arrangement
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Pin designation
Pin(s)
Description
A0 to A8
Address inputs
RAS
Row address strobe
I/O0 to I/O15
Input/output
OE
Output enable
UCAS
Column address strobe, upper byte
LCAS
Column address strobe, lower byte
WE
Read/write control
V
CC
Power (3.3V
0.3V)
GND
Ground
6HOHFWLRQ JXLGH
Symbol
-45
-50
-60
Unit
Maximum RAS access time
t
RAC
45
50
60
ns
Maximum column address access time
t
CAA
20
20
25
ns
Maximum CAS access time
t
CAC
10
10
10
ns
Maximum output enable (OE) access time
t
OEA
10
10
10
ns
Minimum read or write cycle time
t
RC
80
80
100
ns
Minimum EDO page mode cycle time
t
PC
17
17
30
ns
Maximum operating current
I
CC1
60
60
50
mA
Maximum CMOS standby current
I
CC2
200
200
200
A
AS4LC256K16EO
2/25/02; V.1.2
Alliance Semiconductor
P. 2 of 24
)XQFWLRQDO GHVFULSWLRQ
The AS4LC256K16EO is a high-performance 4 megabit CMOS Dynamic Random Access Memory (DRAM) organized as 262,144
words by 16 bits. The AS4LC256K16EO is fabricated with advanced CMOS technology and designed with innovative design
techniques resulting in high speed, extremely low power and wide operating margins at component and system levels.
The AS4LC256K16EO features a high speed page mode operation in which high speed read, write and read-write are performed
on any of the 512
16 bits defined by the column address. The asynchronous column address uses an extremely short row
address capture time to ease the system level timing constraints associated with multiplexed addressing. Very fast
CAS
to output
access time eases system design.
Refresh on the 512 address combinations of A0 to A8 during an 8 ms period is accomplished by performing any of the
following:
RAS-only refresh cycles
Hidden refresh cycles
CAS-before-RAS refresh cycles
Normal read or write cycles
Self refresh cycles
The AS4LC256K16EO is available in standard 40-pin plastic SOJ and 40/44-pin TSOP 2 packages compatible with widely
available automated testing and insertion equipment. System level features include single power supply of 3.3V
0.3V tolerance
and direct interface with TTL logic families.
Logic block diagram
Recommended operating conditions
(T
a
= 0C to +70C)
Parameter
Symbol
Min
Typ
Max
Unit
Supply voltage
V
CC
3.0
3.3
3.6
V
GND
0.0
0.0
0.0
V
Input voltage
V
IH
2.0
V
CC
+ 1
V
V
IL
1.0
0.8
V
REFRESH
CONTR
OLLE
R
51251216
ARRAY
(4,194,304)
SENSE AMP
A0
A1
A2
A3
A4
A5
A6
A7
V
CC
GND
AD
DRES
S BUFF
ERS
A8
R
O
W
DE
CO
DE
R
COLUMN DECODER
RAS CLOCK
GENERATOR
SUBSTRATE
BIAS
GENERATOR
DATA
I/O
BUFFER
OE
RAS
UCAS
WE CLOCK
GENERATOR
WE
LCAS
I/O0 to I/O15
CAS CLOCK
GENERATOR
AS4LC256K16EO
2/25/02; V.1.2
Alliance Semiconductor
P. 3 of 24
$EVROXWH PD[LPXP UDWLQJV
NOTE: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other conditions outside those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
reliability.
DC electrical characteristics
Parameter
Symbol
Min
Max
Unit
Input voltage
V
in
-1.0
+7.0
V
Output voltage
V
out
-1.0
+7.0
V
Power supply voltage
V
CC
-1.0
+7.0
V
Operating temperature
T
OPR
0
+70
C
Storage temperature (plastic)
T
STG
-55
+150
C
Soldering temperature
time
T
SOLDER
260
10
o
C
sec
Power dissipation
P
D
1
W
Short circuit output current
I
out
50
mA
Latch-up current
200
mA
Parameter
Symbol
Test conditions
-45
-50
-60
Unit Note
Min Max Min Max Min Max
Input leakage current
I
IL
0V
V
in
+5.5V
pins not under test = 0V
-10
10
-10
10
-10
10
A
Output leakage current
I
OL
D
OUT
disabled, 0V
V
out
+5.5V
-10
10
-10
10
-10
10
A
Operating power
supply current
I
CC1
RAS, UCAS, LCAS, address cycling; t
RC
=min
60
60
50
mA
1,2
TTL standby power
supply current
I
CC2
RAS = UCAS = LCAS = V
IH
200
200
200
A
Average power supply
current, RAS refresh
mode
I
CC3
RAS cycling, UCAS = LCAS = V
IH
, t
RC
= min
45
45
40
mA
1
EDO page mode average
power supply current
I
CC4
RAS=UCAS=LCAS=V
IL
,
address cycling: t
SC
= min
35
35
35
mA
1,2
CMOS standby power
supply current
I
CC5
RAS=UCAS=LCAS= V
CC
- 0.2V
400
400
400
A
CAS-before-RAS refresh
power supply current
I
CC6
RAS, UCAS, LCAS, cycling; t
RC
= min
50
50
50
mA
1
Output Voltage
V
OH
I
OUT
= -2 mA
2.4
2.4
2.4
V
V
OL
I
OUT
= 2 mA
0.4
0.4
0.4
V
6HOI UHIUHVK FXUUHQW
I
CC7
RAS = UCAS = LCAS=V
IL
,
WE = OE = A0-A8 = V
CC
-0.2V,
DQ0-DQ15 = V
CC
-0.2V, 0.2V are open
-
400
-
400
-
400
A
AS4LC256K16EO
2/25/02; V.1.2
Alliance Semiconductor
P. 4 of 24
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Read cycle
Std Symbol
Parameter
-45
-50
-60
Unit
Notes
Min
Max
Min
Max
Min
Max
t
RC
Random read or write cycle time
80
80
100
ns
t
RP
RAS precharge time
20
20
20
ns
t
RAS
RAS pulse width
45
75K
45
75K
60
75K
ns
t
CAS
CAS pulse width
10
10
10
ns
t
RCD
RAS to CAS delay time
18
32
18
32
15
45
ns
6
t
RAD
RAS to column address delay time
13
23
13
23
15
30
ns
7
t
RSH(R)
CAS to RAS hold time (read cycle)
10
10
12
ns
t
CSH
RAS to CAS hold time
45
50
60
ns
t
CRP
CAS to RAS precharge time
5
5
5
ns
t
ASR
Row address setup time
0
0
0
ns
t
RAH
Row address hold time
8
8
9
ns
t
T
Transition time (rise and fall)
1.5
50
1.5
50
1.5
50
ns
4,5
t
REF
Refresh period
8
8
8
ms
3
t
CLZ
CAS to output in low Z
3
3
3
ns
8
Std Symbol
Parameter
-45
-50
-60
Unit
Notes
Min
Max
Min
Max
Min
Max
t
RAC
Access time from RAS
45
50
60
ns
6
t
CAC
Access time from CAS
10
10
10
ns
6,13
t
AA
Access time from address
22
22
30
ns
7,13
t
AR(R)
Column add hold from RAS
35
35
40
ns
t
RCS
Read command setup time
0
0
0
ns
t
RCH
Read command hold time to CAS
0
0
0
ns
9
tRRH
Read command hold time to RAS
0
0
0
ns
9
t
RAL
Column address to RAS Lead time
25
25
30
ns
t
CPN
CAS precharge time
5
5
5
ns
t
OFF
Output buffer turn-off time
0
10
0
10
0
10
ns
8,10
AS4LC256K16EO
2/25/02; V.1.2
Alliance Semiconductor
P. 5 of 24
:ULWH F\FOH
Read-modify-write cycle
Std Symbol
Parameter
-45
-50
-60
Unit
Notes
Min
Max
Min
Max
Min
Max
t
ASC
Column address setup time
0
0
0
ns
t
CAH
Column address hold time
6
6
10
ns
t
AWR
Column address hold time to RAS
35
35
40
ns
t
WCS
Write command setup time
0
0
0
ns
11
t
WCH
Write command hold time
0
0
0
ns
11
t
WCR
Write command hold time to RAS
35
35
40
ns
t
WP
Write command pulse width
6
6
10
ns
t
RWL
Write command to RAS lead time
12
12
12
ns
t
CWL
Write command to CAS lead time
12
12
12
ns
t
DS
Data-in
setup
time
0
0
0
ns
12
t
DH
Data-in hold time
6
6
10
ns
12
t
DHR
Data-in hold time to RAS
35
35
45
ns
Std Symbol Parameter
-45
-50
-60
Unit
Notes
Min
Max
Min
Max
Min
Max
t
RWC
Read-write
cycle
time
115
115
120
ns
t
RWD
RAS to WE delay time
58
58
60
ns
11
t
CWD
CAS to WE delay time
30
30
30
ns
11
t
AWD
Column address to WE delay time
38
38
40
ns
11
t
RSH(W)
CAS to RAS hold time (write)
10
10
12
ns
t
CAS(W)
CAS pulse width (write)
15
15
15
ns
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