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Электронный компонент: AS6UA51216-BC

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Advance Information
June 2000
Copyright 2000 Alliance Semiconductor. All rights reserved.
AS6UA51216
6/27/00
ALLIANCE SEMICONDUCTOR
1
1.65V to 3.6V 512K16 IntelliwattTM low power CMOS SRAM with one chip enable
Features
AS6UA51216
IntelliwattTM active power circuitry
Industrial and commercial temperature ranges available
Organization: 524,288 words 16 bits
2.7V to 3.6V at 55 ns
2.3V to 2.7V at 70 ns
1.65V to 2.3V at 100 ns
Low power consumption: ACTIVE
- 144 mW at 3.6V and 55 ns
- 68 mW at 2.7V and 70 ns
- 28 mW at 2.3 V and 100 ns
Low power consumption: STANDBY
- 72 W max at 3.6V
- 41
W max at 2.7V
- 28
W max at 2.3V
1.2V data retention
Equal access and cycle times
Easy memory expansion with CS, OE inputs
Smallest footprint packages
- 48-ball FBGA
- 400-mil 44-pin TSOP II
ESD protection
2000 volts
Latch-up current
200 mA
Logic block diagram
512K 16
Array
(8,388,608)
OE
CS
WE
Column decoder
Ro
w
D
e
c
ode
r
A0
A1
A2
A3
A4
A6
A7
A8
V
DD
V
SS
A12
A5
A9
A1
0
A1
1
A1
4
A1
5
A1
6
A1
7
A13
Control circuit
I/O1I/O8
I/O9I/O16
UB
LB
I/O
buffer
A1
8
Pin arrangement (top view)
48-CSP Ball-Grid-Array Package
1
2
3
4
5
6
A
LB
OE
A0
A1
A2
NC
B
I/O9
UB
A3
A4
CS
I/O1
C
I/O10 I/O11
A5
A6
I/O2
I/O3
D
V
SS
I/O12
A17
A7
I/O4
V
CC
E
V
CC
I/O13
V
SS
A16
I/O5
V
SS
F
I/O15 I/O14
A14
A15
I/O6
I/O7
G
I/O16
NC
A12
A13
WE
I/O8
H
A18
A8
A9
A10
A11
NC
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
I/O14
I/O13
V
SS
V
CC
I/O12
I/O11
I/O10
I/O9
A8
A9
A10
A11
A12
A13
A0
CS
I/O1
I/O2
I/O3
I/O4
V
CC
V
SS
I/O5
I/O6
I/O7
I/O8
WE
A18
A17
A16
44-pin 400-mil TSOP II
21
22
A15
A14
UB
LB
I/O16
I/O15
2
A3
3
A2
4
A1
1
A4
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
43
42
41
44
A6
A7
OE
A5
Note: A "MODE" pad is to be placed between pins 33 and 34 and 11 and 12,
shorted. The bonding of this pad to V
CC
or V
SS
configures the device. There should
only be 44+2+2 pads on the chip. Two extra V
CC
to separate out Array from
Peripheral and Two-Mode Pads.
Selection guide
Product
V
CC
Range
Speed
(ns)
Power Dissipation
Min
(V)
Typ
2
(V)
Max
(V)
Operating (I
CC1
)
Standby (I
SB2
)
Max (mA)
Max (
A)
AS6UA51216
2.7
3.0
3.6
55
2
20
AS6UA51216
2.3
2.5
2.7
70
1
15
AS6UA51216
1.65
2.0
2.3
100
1
12
2
ALLIANCE SEMICONDUCTOR
6/27/00
AS6UA51216
Functional description
The AS6UA51216 is a low-power CMOS 8,388,608-bit Static Random Access Memory (SRAM) device organized as 524,288 words 16
bits. It is designed for memory applications where slow data access, low power, and simple interfacing are desired.
Equal address access and cycle times (t
AA
, t
RC
, t
WC
) of 55/70/100 ns are ideal for low-power applications. Active high and low chip enables
(CS) permit easy memory expansion with multiple-bank memory systems.
When CS is high, or UB and LB are high, the device enters standby mode: the AS6UA51216 is guaranteed not to exceed 72
W power
consumption at 3.6V and 55ns; 41
W at 2.7V and 70 ns; or 28
W at 2.3V and 100 ns. The device also returns data when V
CC
is reduced
to 1.5V for even lower power consumption.
A write cycle is accomplished by asserting write enable (WE) and chip enable (CS) low, and UB and/or LB low. Data on the input pins I/O1
O16 is written on the rising edge of WE (write cycle 1) or CS (write cycle 2). To avoid bus contention, external devices should drive I/O
pins only after outputs have been disabled with output enable ( OE) or write enable (WE).
A read cycle is accomplished by asserting output enable (OE), chip enable (CS), UB and LB low, with write enable (WE) high. The chip
drives I/O pins with the data word referenced by the input address. When either chip enable or output enable is inactive, or wri te enable is
active, or (UB) and (LB), output drivers stay in high-impedance mode.
These devices provide multiple center power and ground pins, and separate byte enable controls, allowing individual bytes to be written and
read. LB controls the lower bits, I/O1I/O8, and UB controls the higher bits, I/O9I/O16.
All chip inputs and outputs are CMOS-compatible, and operation is from either a single 1.65V to 3.6V supply. Device is available in the JEDEC
standard 400-mL, TSOP II, and 48-ball FBGA packages.
Absolute maximum ratings
Note: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions outside those indicated in the operational sections of this specificati on is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect reliability.
Truth table
Key: X = Don't care, L = Low, H = High.
Parameter
Device
Symbol
Min
Max
Unit
Voltage on V
CC
relative to V
SS
V
tIN
0.5
V
CC
+ 0.5
V
Voltage on any I/O pin relative to GND
V
tI/O
0.5
V
Power dissipation
P
D
1.0
W
Storage temperature (plastic)
T
stg
65
+150
C
Temperature with V
CC
applied
T
bias
55
+125
C
DC output current (low)
I
OUT
20
mA
CS
WE
OE
LB
UB
Supply
Current
I/O1I/O8 I/O9I/O16
Mode
H
X
X
X
X
I
SB
High Z
High Z
Standby (I
SB
)
L
X
X
H
H
L
H
H
X
X
I
CC
High Z
High Z
Output disable (I
CC
)
L
H
L
L
H
I
CC
D
OUT
High Z
Read (I
CC
)
H
L
High Z
D
OUT
L
L
D
OUT
D
OUT
L
L
X
L
H
I
CC
D
IN
High Z
Write (I
CC
)
H
L
High Z
D
IN
L
L
D
IN
D
IN
AS6UA51216
6/27/00
ALLIANCE SEMICONDUCTOR
3
Recommended operating condition (over the operating range)
Capacitance (f = 1 MHz, T
a
= Room temperature, V
CC
= NOMINAL)
Parameter
Description
Test Conditions
Min
Max
Unit
V
OH
Output HIGH Voltage
I
OH
= 2.1mA
V
CC
= 2.7V
2.4
V
I
OH
= 0.5mA
V
CC
= 2.3V
2.0
I
OH
= 0.1mA
V
CC
= 1.65V
1.5
V
OL
Output LOW Voltage
I
OL
= 2.1mA
V
CC
= 2.7V
0.4
V
I
OL
= 0.5mA
V
CC
= 2.3V
0.4
I
OL
= 0.1mA
V
CC
= 1.65V
0.2
V
IH
Input HIGH Voltage
V
CC
= 2.7V
2.2
V
CC
+ 0.5
V
V
CC
= 2.3V
2.0
V
CC
+ 0.3
V
CC
= 1.65V
1.4
V
CC
+ 0.3
V
IL
Input LOW Voltage
V
CC
= 2.7V
0.5
0.8
V
V
CC
= 2.3V
0.3
0.6
V
CC
= 1.65V
0.3
0.4
I
IX
Input Load Current
GND < V
IN
< V
CC
1
+1
A
I
OZ
Output Load Current
GND < V
O
< V
CC;
Outputs High Z
1
+1
A
I
CC
V
CC
Operating Supply
Current
CS = V
IL
,
V
IN
= V
IL
or V
IH
,
I
OUT
= 0mA,
f = 0
V
CC
= 3.6V
2
mA
V
CC
= 2.7V
1
V
CC
= 2.3V
1
I
CC1
@
1 MHz
Average V
CC
Operating
Supply Current at 1 MHz
CS < 0.2V, V
IN
< 0.2V
or V
IN
> V
CC
0.2V,
f = 1 mS
V
CC
= 3.6V
4
mA
V
CC
= 2.7V
2
V
CC
= 2.3V
2
I
CC2
Average V
CC
Operating
Supply Current
CS
V
IL
, V
IN
= V
IL
or
V
IH
, f = f
Max
V
CC
= 3.6V (55/70/100 mS)
40/30/20
mA
V
CC
= 2.7V (55/70/100 mS)
30/25/15
V
CC
= 2.3V(55/70/100 mS)
25/10/12
I
SB
CS Power Down Current;
TTL Inputs
CS > V
IH
or UB = LB
> V
IH
, other inputs =
V
IL
or V
IH
, f = 0
V
CC
= 3.6V
100
A
V
CC
= 2.7V
100
V
CC
= 2.3V
100
I
SB1
CS Power Down Current;
CMOS Inputs
CS > V
CC
0.2V or
UB = LB > V
CC
0.2V
other inputs = 0V
V
CC
, f = f
Max
V
CC
= 3.6V
20
A
V
CC
= 2.7V
15
V
CC
= 2.3V
12
I
SBDR
Data Retention
CS > V
CC
0.1V,
UB = LB = V
CC
0.1V
f = 0
V
CC
= 1.2V
2
A
Parameter
Symbol
Signals
Test conditions
Max
Unit
Input capacitance
C
IN
A, CS, WE, OE, LB, UB
V
IN
= 0V
5
pF
I/O capacitance
C
I/O
I/O
V
IN
= V
OUT
= 0V
7
pF
4
ALLIANCE SEMICONDUCTOR
6/27/00
AS6UA51216
Read cycle (over the operating range)
Shaded areas indicate preliminary information.
Key to switching waveforms
Read waveform 1 (address controlled)
Read waveform 2 (CS, OE, UB, LB controlled)
Parameter
Symbol
55
70
100
Unit
Notes
Min
Max
Min
Max
Min
Max
Read cycle time
t
RC
55
70
100
ns
Address access time
t
AA
55
70
100
ns
3
Chip enable (CS) access time
t
ACS
55
70
100
ns
3
Output enable (OE) access
time
t
OE
25
35
50
ns
Output hold from address
change
t
OH
10
10
15
ns
5
CS
o output in low Z
t
CLZ
10
10
10
ns
4, 5
CS high to output in high Z
t
CHZ
0
20
0
20
0
20
ns
4, 5
OE low to output in low Z
t
OLZ
5
5
5
ns
4, 5
UB/LB access time
t
BA
55
70
100
ns
UB/LB low to low Z
t
BLZ
10
10
10
ns
4, 5
UB/LB high to high Z
t
BHZ
0
20
0
20
0
20
ns
4, 5
OE high to output in high Z
t
OHZ
0
20
0
20
0
20
ns
4, 5
Power up time
t
PU
0
0
0
ns
4, 5
Power down time
t
PD
55
70
100
ns
4, 5
Undefined/don't care
Falling input
Rising input
t
OH
t
AA
t
RC
t
OH
D
OUT
Address
Data valid
Previous data valid
Data valid
t
RC
t
AA
t
BLZ
t
BA
t
OE
t
OLZ
t
OH
t
OHZ
t
HZ
t
BHZ
t
ACS
t
LZ
Address
OE
CS
LB, UB
D
OUT
AS6UA51216
6/27/00
ALLIANCE SEMICONDUCTOR
5
Write cycle (over the operating range)
Shaded areas indicate preliminary information.
Write waveform 1 (WE controlled)
Write waveform 2 (CS controlled)
Parameter
Symbol
55
70
100
Unit
Notes
Min
Max
Min
Max
Min
Max
Write cycle time
t
WC
55
70
100
ns
Chip enable to write end
t
CW
40
60
80
ns
12
Address setup to write end
t
AW
40
60
80
ns
Address setup time
t
AS
0
0
0
ns
12
Write pulse width
t
WP
35
55
70
ns
Address hold from end of write
t
AH
0
0
0
ns
Data valid to write end
t
DW
25
30
40
ns
Data hold time
t
DH
0
0
0
ns
4, 5
Write enable to output in high Z
t
WZ
0
20
0
20
0
20
ns
4, 5
Output active from write end
t
OW
5
5
5
ns
4, 5
UB/LB low to end of write
t
BW
35
55
70
ns
Address
CS
LB, UB
WE
D
IN
D
OUT
t
WC
t
CW
t
BW
t
AW
t
AS
t
WP
t
DW
t
DH
t
OW
t
WZ
t
AH
Data undefined
High Z
Data valid
Address
CS
LB, UB
WE
D
IN
t
WC
t
CW
t
BW
t
WP
t
DW
t
DH
t
OW
t
WZ
t
AH
D
OUT
Data undefined
High Z
High Z
t
AS
t
AW
Data valid
t
CLZ