October 2000
Copyright 2000 Alliance Semiconductor. All rights reserved.
AS6VA25616
10/6/00
ALLIANCE SEMICONDUCTOR
1
2.7V to 3.3V 256K 16 IntelliwattTM low-power CMOS SRAM with one chip enable
Features
AS6VA25616
IntelliwattTM active power circuitry
Industrial and commercial temperature ranges available
Organization: 262,144 words 16 bits
2.7V to 3.3V at 55 ns
Low power consumption: ACTIVE
- 132 mW at 3.3V and 55 ns
Low power consumption: STANDBY
- 66 W max at 3.3V
1.2V data retention
Equal access and cycle times
Easy memory expansion with CS, OE inputs
Smallest footprint packages
- 48-ball FBGA
- 400-mil 44-pin TSOP II
ESD protection
2000 volts
Latch-up current
200 mA
Logic block diagram
256K 16
Array
(4,194,304)
OE
CS
WE
Column decoder
Ro
w De
c
o
d
e
r
A0
A1
A2
A3
A4
A6
A7
A8
V
CC
V
SS
A12
A5
A9
A1
0
A1
1
A1
4
A1
5
A1
6
A1
7
A13
Control circuit
I/O1I/O8
I/O9I/O16
UB
LB
I/O
buffer
Pin arrangement (top view)
48-CSP Ball-Grid-Array Package
1
2
3
4
5
6
A
LB
OE
A0
A1
A2
NC
B
I/O9
UB
A3
A4
CS
I/O1
C
I/O10 I/O11
A5
A6
I/O2
I/O3
D
V
SS
I/O12
A17
A7
I/O4
V
CC
E
V
CC
I/O13
NC
A16
I/O5
V
SS
F
I/O15 I/O14
A14
A15
I/O6
I/O7
G
I/O16
NC
A12
A13
WE
I/O8
H
NC
A8
A9
A10
A11
NC
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
I/O14
I/O13
V
SS
V
CC
I/O12
I/O11
I/O10
I/O9
NC
A8
A9
A10
A11
A12
A0
CS
I/O1
I/O2
I/O3
I/O4
V
CC
V
SS
I/O5
I/O6
I/O7
I/O8
WE
A17
A16
A15
44-pin 400-mil TSOP II
21
22
A14
A13
UB
LB
I/O16
I/O15
2
A3
3
A2
4
A1
1
A4
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
43
42
41
44
A6
A7
OE
A5
Selection guide
Product
V
CC
Range
Speed
(ns)
Power Dissipation
Min
(V)
Typ
2
(V)
Max
(V)
Operating (I
CC
)
Standby (I
SB1
)
Max (mA)
Max (
A)
AS6VA25616
2.7
3.0
3.3
55
2
20
2
ALLIANCE SEMICONDUCTOR
10/6/00
AS6VA25616
Functional description
The AS6VA25616 is a low-power CMOS 4,194,304-bit Static Random Access Memory (SRAM) device organized as 262,144 words 16
bits. It is designed for memory applications where slow data access, low power, and simple interfacing are desired.
Equal address access and cycle times (t
AA
, t
RC
, t
WC
) of 55 ns are ideal for low-power applications. Active high and low chip selects (CS)
permit easy memory expansion with multiple-bank memory systems.
When CS is high, or UB and LB are high, the device enters standby mode: the AS6VA25616 is guaranteed not to exceed 66
W power
consumption at 3.3V and 55 ns. The device also returns data when V
CC
is reduced to 1.5V for even lower power consumption.
A write cycle is accomplished by asserting write enable (WE) and chip select (CS) low, and UB and/or LB low. Data on the input pins
I/O1O16 is written on the rising edge of WE (write cycle 1) or CS (write cycle 2). To avoid bus contention, external devices should drive
I/O pins only after outputs have been disabled with output enable (OE) or write enable (WE).
A read cycle is accomplished by asserting output enable (OE), chip select (CS), UB and LB low, with write enable (WE) high. The chip
drives I/O pins with the data word referenced by the input address. When either chip select or output enable is inactive, or write enable is
active, or (UB) and (LB), output drivers stay in high-impedance mode.
These devices provide multiple center power and ground pins, and separate byte enable controls, allowing individual bytes to be written
and read. LB controls the lower bits, I/O1I/O8, and UB controls the higher bits, I/O9I/O16.
All chip inputs and outputs are CMOS-compatible, and operation is from a single 2.7V to 3.3V supply. Device is available in the JEDEC
standard 400-mm, TSOP II, and 48-ball FBGA packages.
Absolute maximum ratings
Note: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Truth table
Key: X = Don't care, L = Low, H = High.
Parameter
Device
Symbol
Min
Max
Unit
Voltage on V
CC
relative to V
SS
V
tIN
0.5
V
CC
+ 0.5
V
Voltage on any I/O pin relative to GND
V
tI/O
0.5
V
Power dissipation
P
D
1.0
W
Storage temperature (plastic)
T
stg
65
+150
o
C
Temperature with V
CC
applied
T
bias
55
+125
o
C
DC output current (low)
I
OUT
20
mA
CS
WE
OE
LB
UB
Supply
Current
I/O1I/O8
I/O9I/O16
Mode
H
X
X
X
X
I
SB
High Z
High Z
Standby (I
SB
)
L
X
X
H
H
L
H
H
X
X
I
CC
High Z
High Z
Output disable (I
CC
)
L
H
L
L
H
I
CC
D
OUT
High Z
Read (I
CC
)
H
L
High Z
D
OUT
L
L
D
OUT
D
OUT
L
L
X
L
H
I
CC
D
IN
High Z
Write (I
CC
)
H
L
High Z
D
IN
L
L
D
IN
D
IN
4
ALLIANCE SEMICONDUCTOR
10/6/00
AS6VA25616
Read cycle (over the operating range)
3,9
Shaded areas indicate preliminary information.
Key to switching waveforms
Read waveform 1 (address controlled)
3,6,7,9
Read waveform 2 (CS, OE, UB, LB controlled)
3,6,8,9
Parameter
Symbol
Min
Max
Unit
Notes
Read cycle time
t
RC
55
ns
Address access time
t
AA
55
ns
3
Chip select (
CS
) access time
t
ACS
55
ns
3
Output enable (
OE
) access time
t
OE
25
ns
Output hold from address change
t
OH
10
ns
5
CS
low t
o output in low Z
t
CLZ
10
ns
4, 5
CS
high to output in high Z
t
CHZ
0
20
ns
4, 5
OE
low to output in low Z
t
OLZ
5
ns
4, 5
UB/LB access time
t
BA
55
ns
UB/LB low to low Z
t
BLZ
10
ns
4, 5
UB/LB high to high Z
t
BHZ
0
20
ns
4, 5
OE
high to output in high Z
t
OHZ
0
20
ns
4, 5
Power up time
t
PU
0
ns
4, 5
Power down time
t
PD
55
ns
4, 5
Undefined/don't care
Falling input
Rising input
t
OH
t
AA
t
RC
t
OH
D
OUT
Address
Data valid
Previous data valid
Data valid
t
RC
t
AA
t
BLZ
t
BA
t
OE
t
OLZ
t
OH
t
OHZ
t
HZ
t
BHZ
t
ACS
t
LZ
Address
OE
CS
LB, UB
D
OUT
AS6VA25616
10/6/00
ALLIANCE SEMICONDUCTOR
5
Write cycle (over the operating range)
11
Shaded areas indicate preliminary information.
Write waveform 1 (WE controlled)
10,11
Write waveform 2 (CS controlled)
10,11
Parameter
Symbol
Min
Max
Unit
Notes
Write cycle time
t
WC
55
ns
Chip select to write end
t
CW
40
ns
12
Address setup to write end
t
AW
40
ns
Address setup time
t
AS
0
ns
12
Write pulse width
t
WP
35
ns
Address hold from end of write
t
AH
0
ns
Data valid to write end
t
DW
25
ns
Data hold time
t
DH
0
ns
4, 5
Write enable to output in high Z
t
WZ
0
20
ns
4, 5
Output active from write end
t
OW
5
ns
4, 5
UB/LB low to end of write
t
BW
35
ns
Address
CS
LB, UB
WE
D
IN
D
OUT
t
WC
t
CW
t
BW
t
AW
t
AS
t
WP
t
DW
t
DH
t
OW
t
WZ
t
AH
Data undefined
High Z
Data valid
Address
CS
LB, UB
WE
D
IN
t
WC
t
CW
t
BW
t
WP
t
DW
t
DH
t
OW
t
WZ
t
AH
D
OUT
Data undefined
High Z
High Z
t
AS
t
AW
Data valid
t
CLZ
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