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Электронный компонент: AS7C31026B-20JI

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March 2004
Copyright Alliance Semiconductor. All rights reserved.
AS7C31026B
3.3 V 64K X 16 CMOS SRAM
3/26/04, v 1.3
Alliance Semiconductor
P. 1 of 10
Features
Industrial and commercial versions
Organization: 65,536 words 16 bits
Center power and ground pins for low noise
High speed
- 10/12/15/20 ns address access time
- 5, 6, 7, 8 ns output enable access time
Low power consumption: ACTIVE
- 288 mW / max @ 10 ns
Low power consumption: STANDBY
- 18 mW / max CMOS I/O
6 T 0.18 u CMOS technology
Easy memory expansion with
CE
,
OE
inputs
TTL-compatible, three-state I/O
JEDEC standard packaging
- 44-pin 400 mil SOJ
- 44-pin TSOP 2-400
ESD protection
2000 volts
Latch-up current
200 mA
Logic block diagram
64 K 16
Array
OE
CE
WE
Column decoder
Ro
w
decod
er
A0
A1
A2
A3
A4
A5
A7
V
CC
GND
A8
A9
A1
0
A1
1
A1
2
A1
3
A1
4
A1
5
Control circuit
I/O0I/O7
I/O8I/O15
UB
LB
I/O
buffer
A6
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
I/O13
I/O12
GND
V
CC
I/O11
I/O10
I/O9
I/O8
NC
A8
A9
A10
A11
NC
A0
CE
I/O0
I/O1
I/O2
I/O3
V
CC
GND
I/O4
I/O5
I/O6
I/O7
WE
A15
A14
A13
44-Pin SOJ (400 mil), TSOP 2
21
22
A12
NC
UB
LB
I/O15
I/O14
2
A3
3
A2
4
A1
1
A4
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
43
42
41
44
A6
A7
OE
A5
AS7C3102
6B
Selection guide
-10
-12
-15
-20
Unit
Maximum address access time
10
12
15
20
ns
Maximum output enable access time
5
6
7
8
ns
Maximum operating current
80
75
70
65
mA
Maximum CMOS standby current
5
5
5
5
mA
Pin arrangement
AS7C31026B
3/26/04, v 1.3
Alliance Semiconductor
P. 2 of 10
Functional description
The AS7C31026B is a high-performance CMOS 1,048,576-bit Static Random Access Memory (SRAM) device organized as 65,536 words
16 bits. It is designed for memory applications where fast data access, low power, and simple interfacing are desired.
Equal address access and cycle times (t
AA
, t
RC
, t
WC
) of 10/12/15/20 ns with output enable access times (t
OE
) of 5, 6, 7, 8 ns are ideal for
high-performance applications.
When CE is high, the device enters standby mode.
A write cycle is accomplished by asserting write enable (WE) and chip enable (CE). Data
on the input pins I/O0 through I/O15 is written on the rising edge of WE (write cycle 1) or CE (write cycle 2). To avoid bus contention,
external devices should drive I/O pins only after outputs have been disabled with output enable (OE) or write enable (WE).
A read cycle is accomplished by asserting output enable (OE) and chip enable (CE) with write enable (WE) high. The chips drive I/O pins
with the data word referenced by the input address. When either chip enable or output enable is inactive or write enable is active, output
drivers stay in high-impedance mode.
The device provides multiple center power and ground pins, and separate byte enable controls, allowing individual bytes to be written and
read. LB controls the lower bits, I/O0 through I/O7, and UB controls the higher bits, I/O8 through I/O15.
All chip inputs and outputs are TTL-compatible, and operation is from a single 3.3 V supply. The device is packaged in common industry
standard packages.
Note: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and func-
tional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect reliability.
Key:
H = high, L = low, X = don't care.
Absolute maximum ratings
Parameter
Symbol
Min
Max
Unit
Voltage on V
CC
relative to GND
V
t1
0.50
+5.0
V
Voltage on any pin relative to GND
V
t2
0.50
V
CC
+0.50
V
Power dissipation
P
D
1.0
W
Storage temperature (plastic)
T
stg
65
+150
C
Ambient temperature with VCC applied
T
bias
55
+125
C
DC current into outputs (low)
I
OUT
20
mA
Truth table
CE
WE
OE
LB
UB
I/O0I/O7
I/O8I/O15
Mode
H
X
X
X
X
High Z
High Z
Standby (I
SB
), I
SBI
)
L
H
L
L
H
D
OUT
High Z
Read I/O0I/O7 (I
CC
)
L
H
L
H
L
High Z
D
OUT
Read I/O8I/O15 (I
CC)
L
H
L
L
L
D
OUT
D
OUT
Read I/O0I/O15 (I
CC
)
L
L
X
L
L
D
IN
D
IN
Write I/O0I/O15 (I
CC
)
L
L
X
L
H
D
IN
High Z
Write I/O0I/O7 (I
CC
)
L
L
X
H
L
High Z
D
IN
Write I/O8I/O15 (I
CC
)
L
L
H
X
H
X
X
H
X
H
High Z
High Z
Output disable (I
CC
)
AS7C31026B
3/26/04, v 1.3
Alliance Semiconductor
P. 3 of 10
V
IL
= -1.0V for pulse width less than 5ns
V
IH =
V
CC
+ 1.5V for pulse width less than 5ns
Recommended operating conditions
Parameter
Symbol
Min
Nominal
Max
Unit
Supply voltage
V
CC
3.0
3.3
3.6
V
Input voltage
V
IH
2.0
V
CC
+ 0.5
V
V
IL
0.5
0.8
V
Ambient operating temperature
commercial
T
A
0
70
o
C
industrial
T
A
40
85
o
C
DC operating characteristics (over the operating range)
1
Parameter
Sym
Test conditions
-10
-12
-15
-20
Unit
Min Max Min Max Min
Max
Min
Max
Input leakage
current
| I
LI
|
V
CC
= Max
V
IN
= GND to V
CC
1
1
1
1
A
Output leakage
current
| I
LO
|
V
CC
= Max
CE = V
IH
,
V
OUT
= GND to V
CC
1
1
1
1
A
Operating power
supply current
I
CC
V
CC
= Max,
CE
V
IL
, I
OUT
= 0mA
f = f
Max
80
75
70
65
mA
Standby
power supply
current
I
SB
V
CC
= Max,
CE
V
IH
, f = f
Max
30
25
20
20
mA
I
SB1
V
CC
= Max, CE
V
CC
0.2 V,
V
IN
0.2 V or
V
IN
V
CC
0.2 V, f = 0
5
5
5
5
mA
Output
voltage
V
OL
I
OL
= 8 mA, V
CC
= Min
0.4
0.4
0.4
0.4
V
V
OH
I
OH
= 4 mA, V
CC
= Min
2.4
2.4
2.4
2.4
V
Capacitance (f = 1MHz, T
a
= 25
C, V
CC
= NOMINAL)
2
Parameter
Symbol
Signals
Test conditions
Max
Unit
Input capacitance
C
IN
A, CE, WE, OE, LB, UB
V
IN
= 0 V
5
pF
I/O capacitance
C
I/O
I/O
V
IN
= V
OUT
= 0 V
7
pF
AS7C31026B
3/26/04, v 1.3
Alliance Semiconductor
P. 4 of 10
Key to switching waveforms
Read waveform 1 (address controlled)
3,6,7,9
Read cycle (over the operating range)
3,9
Parameter
Symbol
-10
-12
-15
-20
Unit Notes
Min
Max
Min
Max
Min
Max
Min
Max
Read cycle time
t
RC
10
12
15
20
ns
Address access time
t
AA
10
12
15
20
ns
3
Chip enable (CE) access time
t
ACE
10
12
15
20
ns
3
Output enable (OE) access time
t
OE
5
6
7
8
ns
Output hold from address change
t
OH
3
3
3
3
ns
5
CE low to output in low Z
t
CLZ
3
3
3
3
ns
4, 5
CE high to output in high Z
t
CHZ
3
3
4
5
ns
4, 5
OE low to output in low Z
t
OLZ
0
0
0
0
ns
4, 5
Byte select access time
t
BA
5
6
7
8
ns
Byte select Low to low Z
t
BLZ
0
0
0
0
ns
4, 5
Byte select High to high Z
t
BHZ
5
6
6
8
ns
4, 5
OE high to output in high Z
t
OHZ
5
6
7
8
ns
4, 5
Power up time
t
PU
0
0
0
0
ns
4, 5
Power down time
t
PD
10
12
15
20
ns
4, 5
Undefined output/don't care
Falling input
Rising input
t
OH
t
AA
t
RC
t
OH
Data
OUT
Address
Data valid
Previous data valid
AS7C31026B
3/26/04, v 1.3
Alliance Semiconductor
P. 5 of 10
Read waveform 2 (OE, CE, UB, LB controlled)
3,6,8,9
Write cycle (over the operating range)
11
Parameter
Symbol
-10
-12
-15
-20
Unit
Notes
Min Max Min Max Min Max Min Max
Write cycle time
t
WC
10
12
15
20
ns
Chip enable (CE) to write end
t
CW
8
9
10
12
ns
Address setup to write end
t
AW
8
9
10
12
ns
Address setup time
t
AS
0
0
0
0
ns
Write pulse width
t
WP
7
8
9
12
ns
Write recovery time
t
WR
0
0
0
0
ns
Address hold from end of write
t
AH
0
0
0
0
ns
Data valid to write end
t
DW
5
6
8
10
ns
Data hold time
t
DH
0
0
0
0
ns
5
Write enable to output in high Z
t
WZ
5
6
7
8
ns
4, 5
Output active from write end
t
OW
1
1
1
2
ns
4, 5
Byte select low to end of write
t
BW
7
8
9
9
ns
Data valid
t
RC
t
AA
t
BLZ
t
BA
t
OE
t
OLZ
t
OH
t
OHZ
t
HZ
t
BHZ
t
ACE
t
LZ
Address
OE
CE
LB, UB
Data
IN
AS7C31026B
3/26/04, v 1.3
Alliance Semiconductor
P. 6 of 10
Write waveform 1 (WE controlled)
10,11
Write waveform 2 (CE controlled)
10,11
Address
CE
LB, UB
WE
Data
IN
Data
OUT
t
WC
t
CW
t
BW
t
AW
t
AS
t
WP
t
DW
t
DH
t
OW
t
WZ
t
WR
Data undefined
high Z
Data valid
t
AH
Address
CE
LB, UB
WE
Data
IN
t
WC
t
CW
t
BW
t
WP
t
DW
t
DH
t
OW
t
WZ
t
WR
Data
OUT
Data undefined
high Z
high Z
t
AS
t
AW
Data valid
t
CLZ
t
AH
AS7C31026B
3/26/04, v 1.3
Alliance Semiconductor
P. 7 of 10
AC test conditions
Notes
1
During V
CC
power-up, a pull-up resistor to V
CC
on CE is required to meet I
SB
specification.
2
This parameter is sampled, but not 100% tested.
3
For test conditions, see AC Test Conditions, Figures A and B.
4
These parameters are specified with C
L
= 5 pF, as in Figures B. Transition is measured 500 mV from steady-state voltage.
5
This parameter is guaranteed, but not tested.
6
WE is high for read cycle.
7
CE and OE are low for read cycle.
8
Address is valid prior to or coincident with CE transition low.
9
All read cycle timings are referenced from the last valid address to the first transitioning address.
10 N/A
11 All write cycle timings are referenced from the last valid address to the first transitioning address.
12 Not applicable.
13 C = 30 pF, except all high Z and low Z parameters where C = 5 pF.
255
C
13
320
GND
+3.3 V
Figure B: 3.3 V Output load
168
Thevenin Equivalent:
D
OUT
+1.728 V
10%
90%
10%
90%
GND
+3.0 V
Figure A: Input pulse
2 ns
D
OUT
Output load: see Figure B.
Input pulse level: GND to 3.0 V. See Figure A.
Input rise and fall times: 2 ns. See Figure A.
Input and output timing reference levels: 1.5
AS7C31026B
3/26/04, v 1.3
Alliance Semiconductor
P. 8 of 10
Package dimensions
44-pin TSOP 2
Min
(mm)
Max
(mm)
A
1.2
A1
0.05
0.15
A2
0.95
1.05
b
0.30
0.45
c
0.120
0.21
D
18.31
18.52
E
10.06
10.26
He
11.68
11.94
e
0.80 (typical)
l
0.40
0.60
D
He
1 2 3 4 5 6 7 8 9 10 11 12 13 14
44 43 42 41 40 39 38 37 36 35 34 33 32 31
15 16
30 29
17 18 19 20
28 27 26 25
c
l
A1
A2
e
44-pin TSOP 2
05
21
24
22
23
E
A
b
Seating
plane
44-pin SOJ
44-pin SOJ
400 mil
Min (in) Max (in)
A
0.128
0.148
A
1
0.025
A
2
0.105
0.115
B
0.026
0.032
b
0.015
0.020
c
0.007
0.013
D
1.120
1.130
E
0.370 NOM
E
1
0.395
0.405
E
2
0.435
0.445
e
0.050 NOM
e
Pin 1
A
1
b
B
A
A
2
E
2
E
1
D
c
E
AS7C31026B
3/26/04, v 1.3
Alliance Semiconductor
P. 9 of 10
Note:
Add suffix `N' to the above part number for lead free parts (Ex.
AS7C31026B-10JCN)
Ordering codes
Package\Access time
Volt/Temp
10 ns
12 ns
15 ns
20 ns
Plastic SOJ, 400 mil
3.3 V commercial AS7C31026B-10JC
AS7C31026B-12JC
AS7C31026B-15JC
AS7C31026B-20JC
3.3 V industrial
AS7C31026B-10JI
AS7C31026B-12JI
AS7C31026B-15JI
AS7C31026B-20JI
TSOP 2, 10.2 x 18.4 mm
3.3 V commercial AS7C31026B-10TC AS7C31026B-12TC AS7C31026B-15TC AS7C31026B-20TC
3.3 V industrial
AS7C31026B-10TI
AS7C31026B-12TI
AS7C31026B-15TI
AS7C31026B-20TI
Part numbering system
AS7C
X
1026B
XX
X
X
X
SRAM
prefix
Voltage:
3 = 3.3 V CMOS
Device
number
Access
time
Package:
J = SOJ 400 mil
T = TSOP 2, 10.2 x 18.4 mm
Temperature range:
C = commercial: 0 C to 70 C
I = industrial: -40 C to 85 C
N=Lead Free
Part
Alliance Semiconductor Corporation
2575, Augustine Drive,
Santa Clara, CA 95054
Tel: 408 - 855 - 4900
Fax: 408 - 855 - 4999
www.alsc.com
Copyright Alliance Semiconductor
All Rights Reserved
Part Number: AS7C31026B
Document Version: v 1.3
Copyright 2003 Alliance Semiconductor Corporation. All rights reserved. Our three-point logo, our name and Intelliwatt are trademarks or registered
trademarks of Alliance. All other brand and product names may be the trademarks of their respective companies. Alliance reserves the right to make
changes to this document and its products at any time without notice. Alliance assumes no responsibility for any errors that may appear in this document.
The data contained herein represents Alliance's best data and/or estimates at the time of issuance. Alliance reserves the right to change or correct this
data at any time, without notice. If the product described herein is under development, significant changes to these specifications are possible. The
information in this product data sheet is intended to be general descriptive information for potential customers and users, and is not intended to operate
as, or provide, any guarantee or warrantee to any user or customer. Alliance does not assume any responsibility or liability arising out of the application
or use of any product described herein, and disclaims any express or implied warranties related to the sale and/or use of Alliance products including
liability or warranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual property rights, except as express
agreed to in Alliance's Terms and Conditions of Sale (which are available from Alliance). All sales of Alliance products are made exclusively according
to Alliance's Terms and Conditions of Sale. The purchase of products from Alliance does not convey a license under any patent rights, copyrights; mask
works rights, trademarks, or any other intellectual property rights of Alliance or third parties. Alliance does not authorize its products for use as critical
components in life-supporting systems where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the
inclusion of Alliance products in such life-supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify
Alliance against all claims arising from such use.
AS7C31026B