Document Outline
- Features
- Logic block diagram
- Pin arrangement for TSOP 2
- Selection guide
- Functional description
- Absolute maximum ratings
- Truth table
- Recommended operating conditions
- DC operating characteristics (over the operating range)1
- Capacitance (f = 1MHz, Ta = 25 C, VCC = NOMINAL)4
- Read cycle (over the operating range)2,8
- Key to switching waveforms
- Read waveform 1 (address controlled)5,6,8
- Read waveform 2 (CE, OE, UB, LB controlled)5,7,8
- Write cycle (over the operating range)9
- Write waveform 1(WE controlled)9
- Write waveform 2 (CE controlled)9
- Write waveform 3 9
- AC test conditions
- Ordering Codes
- Part numbering system
February 2005
Preliminary Information
Copyright Alliance Semiconductor. All rights reserved.
AS7C32098A
3.3 V 128K 16 CMOS SRAM
2/24/05, v. 1.0
Alliance Semiconductor
P. 1 of 10
Features
Industrial and commercial temperature
Organization: 131,072 words 16 bits
Center power and ground pins
High speed
- 10/12/15/20 ns address access time
- 4/5/6/7 ns output enable access time
Low power consumption: ACTIVE
- 650 mW /max @ 10 ns
Low power consumption: STANDBY
- 28.8 mW /max CMOS
Individual byte read/write controls
Easy memory expansion with CE, OE inputs
TTL- and CMOS-compatible, three-state I/O
44-pin JEDEC standard packages
- TSOP 2
ESD protection
2000 volts
Latch-up current
200 mA
Logic block diagram
1024 128 16
Array
(2,097,152)
OE
CE
WE
Column decoder
Ro
w D
e
c
o
d
e
r
A0
A1
A2
A3
A4
A6
A7
A8
V
CC
GND
A12
A5 A9 A10 A1
1
A14 A15 A16
A13
Control circuit
I/O1I/O8
I/O9I/O16
UB
LB
I/O
buffer
Pin arrangement for TSOP 2
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
I/O14
I/O13
GND
V
CC
I/O12
I/O11
I/O10
I/O9
NC
A13
A12
A11
A10
NC
A4
CE
I/O1
I/O2
I/O3
I/O4
V
CC
GND
I/O5
I/O6
I/O7
I/O8
WE
A5
A6
A7
21
22
A8
A9
UB
LB
I/O16
I/O15
2
A1
3
A2
4
A3
1
A0
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
43
42
41
44
A15
A14
OE
A16
Selection guide
10
12
15
20
Unit
Maximum address access time
10
12
15
20
ns
Maximum output enable access time
4
5
6
7
ns
Maximum operating current
Industrial
180
160
140
110
mA
Commercial
170
150
130
100
mA
Maximum CMOS standby current
8
8
8
8
mA
AS7C32098A
2/24/05,v. 1.0
Alliance Semiconductor
P. 2 of 10
Functional description
The AS7C32098A is a high-performance CMOS 2,097,152-bit Static Random Access Memory (SRAM) device organized as
131,072 words 16 bits. It is designed for memory applications where fast data access, low power, and simple interfacing are
desired.
Equal address access and cycle times (t
AA
, t
RC
, t
WC
) of 10/12/15/20 ns with output enable access times (t
OE
) of 4/5/6/7 ns are
ideal for high-performance applications. The chip enable input CE permits easy memory expansion with multiple-bank
memory systems.
When CE is high the device enters standby mode. The device is guaranteed not to exceed 28.8mW power consumption in
CMOS standby mode. A write cycle is accomplished by asserting write enable (WE) and chip enable (CE). Data on the input
pins I/O1I/O16 is written on the rising edge of WE (write cycle 1) or CE (write cycle 2). To avoid bus contention, external
devices should drive I/O pins only after outputs have been disabled with output enable (OE) or write enable (WE).
A read cycle is accomplished by asserting output enable (OE) and chip enable (CE), with write enable (WE) high. The chip
drives I/O pins with the data word referenced by the input address. When either chip enable or output enable is inactive, or
write enable is active, output drivers stay in high-impedance mode.
The device provides multiple center power and ground pins, and separate byte enable controls, allowing individual bytes to be
written and read. LB controls the lower bits, I/O1I/O8, and UB controls the higher bits, I/O9I/O16.
All chip inputs and outputs are TTL- and CMOS-compatible, and operation is for 3.3V (AS7C32098A) supply. The device is
available in the JEDEC standard TSOP 2 package.
Note: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Absolute maximum ratings
Parameter
Symbol
Min
Max
Unit
Voltage on V
CC
relative to GND
V
t1
0.50
+5.0
V
Voltage on any pin relative to GND
V
t2
0.50
V
CC
+0.50
V
Power dissipation
P
D
1.5
W
Storage temperature (plastic)
T
stg
65
+150
C
Ambient temperature with V
CC
applied
T
bias
55 +125
C
DC current into outputs (low)
I
OUT
20
mA
Truth table
CE
WE
OE
LB
UB
I/O1I/O8
I/O9I/O16
Mode
H
X
X
X
X
High Z
High Z
Standby (I
SB
, I
SB1
)
L
H
H
X
X
High Z
High Z
Output disable (I
CC
)
L
X
X
H
H
L
H
L
L
H
D
OUT
High Z
Read (I
CC
)
H
L
High Z
D
OUT
L
L
D
OUT
D
OUT
L
L
X
L
H
D
IN
High Z
Write (I
CC
)
H
L
High Z
D
IN
L
L
D
IN
D
IN
Key: X = Don't care, L = Low, H = High.
AS7C32098A
2/24/05,v. 1.0
Alliance Semiconductor
P. 3 of 10
Recommended operating conditions
Parameter
Symbol
Min Typical
Max
Unit
Supply voltage
V
CC
(10/12/15/20)
3.0
3.3
3.6
V
Input voltage
V
IH
**
2.0
V
CC
+ 0.5
V
V
IL
*
0.5
0.8
V
Ambient operating temperature
commercial
T
A
0
70
C
industrial
T
A
40
85
C
* V
IL
min = 1.0V for pulse width less than 5ns.
** V
IH
max = V
CC
+ 2.0V for pulse width less than 5ns.
DC operating characteristics (over the operating range)
1
Parameter
Symbol
Test conditions
10
12
15
20
Unit
Min Max Min Max Min Max Min Max
Input leakage
current
|I
LI
|
V
CC
= Max
V
IN
= GND to V
CC
1
1
1
1
A
Output leakage
current
|I
LO
|
V
CC
= Max
CE = V
IH
or OE = V
IH
or WE = V
IL
V
I/O
= GND to V
CC
1
1
1
1
A
Operating
power supply
current
I
CC
V
CC
= Max
CE
V
IL
, f = f
max
I
OUT
= 0mA
Industrial
180
160
140
110 mA
Commercial
-
170
-
150
-
130
-
100 mA
Standby power
supply current
I
SB
V
CC
= Max
CE
V
IH
, f = Max
60
60
60
60
mA
I
SB1
V
CC
= Max
CE
V
CC
0.2V, V
IN
V
CC
0.2V or
V
IN
0.2V, f = 0
8
8
8
8
mA
Output voltage
V
OL
I
OL
= 8 mA, V
CC
= Min
0.4
0.4
0.4
0.4
V
V
OH
I
OH
= 4 mA, V
CC
= Min
2.4
2.4
2.4
2.4
V
Capacitance (f = 1MHz, T
a
= 25
C, V
CC
= NOMINAL)
4
Parameter
Symbol
Signals
Test conditions
Max
Unit
Input capacitance
C
IN
A, CE, WE, OE, UB, LB
V
IN
= 0V
6
pF
I/O capacitance
C
I/O
I/O
V
IN
= V
OUT
= 0V
8
pF
AS7C32098A
2/24/05,v. 1.0
Alliance Semiconductor
P. 4 of 10
Key to switching waveforms
Read waveform 1 (address controlled)
5,6,8
Read cycle (over the operating range)
2,8
Parameter
Symbol
10
12
15
20
Unit Notes
Min
Max
Min Max Min Max Min Max
Read cycle time
t
RC
10
12
15
20
ns
Address access time
t
AA
10
12
15
20
ns
Chip enable (CE) access time
t
ACE
10
12
15
20
ns
Output enable (OE) access time
t
OE
4
5
6
7
ns
Output hold from address change
t
OH
3
3
3
3
ns
4
CE Low to output in low Z
t
CLZ
3
3
3
3
ns
3,4
CE High to output in high Z
t
CHZ
5
6
7
9
ns
3,4
OE Low to output in low Z
t
OLZ
0
0
0
0
ns
3,4
OE High to output in high Z
t
OHZ
5
6
7
9
ns
3,4
LB, UB access time
t
BA
5
6
7
8
ns
LB, UB Low to output in low Z
t
BLZ
0
0
0
0
ns
LB, UB High to output in high Z
t
BHZ
5
6
7
9
ns
Power up time
t
PU
0
0
0
0
ns
4
Power down time
t
PD
10
12
15
20
ns
4
Undefined/don't care
Falling input
Rising input
t
OH
t
AA
t
RC
t
OH
Data
OUT
Address
Data valid
Previous data valid
AS7C32098A
2/24/05,v. 1.0
Alliance Semiconductor
P. 5 of 10
Read waveform 2 (CE, OE, UB, LB controlled)
5,7,8
Write cycle (over the operating range)
9
Parameter
Symbol
10
12
15
20
Unit Note
Min
Max
Min
Max
Min
Max
Min
Max
Write cycle time
t
WC
10
12
15
20
ns
Chip enable (CE) to write end
t
CW
7
8
10
12
ns
Address setup to write end
t
AW
7
8
10
12
ns
Address setup time
t
AS
0
0
0
0
ns
Write pulse width (OE = High)
t
WP1
7
8
10
12
ns
Write pulse width (OE = Low)
t
WP2
10
12
15
20
ns
Write recovery time
t
WR
0
0
0
0
ns
Address hold from end of write
t
AH
0
0
0
0
ns
Data valid to write end
t
DW
5
6
7
9
ns
Data hold time
t
DH
0
0
0
0
ns
3,4
Write enable to output in High-Z
t
WZ
0
5
0
6
0
7
0
9
ns
3,4
Output active from write end
t
OW
3
3
3
3
ns
3,4
Byte enable Low to write end
t
BW
7
8
10
12
ns
3,4
Data valid
t
RC
t
AA
t
BLZ
t
BA
t
OE
t
OLZ
t
OH
t
OHZ
t
CHZ
t
BHZ
t
ACE
t
CLZ
Address
OE
CE
LB, UB
Data
OUT
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