December 2002
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AS7C33128NTD32A
AS7C33128NTD36A
9 . 65$0 ZLWK 17'
TM
Y
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Features
Organization: 131,072 words 32 or 36 bits NTD
TM1
architecture for efficient bus operation
Fast clock speeds to 166 MHz in LVTTL/LVCMOS
Fast clock to data access: 3.5/4.0/5.0 ns
Fast OE access time: 3.5/4.0/5.0 ns
Fully synchronous operation
Flow-through or pipelined mode
Asynchronous output enable control
1. NTD
TM
is a trademark of Alliance Semiconductor Corporation.
Economical 100-pin TQFP package
Byte write enables
Clock enable for operation hold
Multiple chip enables for easy expansion
3.3V core power supply
2.5V or 3.3V I/O operation with separate V
DDQ
30 mW typical standby power
Self-timed write cycles
Interleaved or linear burst modes
Snooze mode for standby operation
Wr
i
t
e
D
a
t
a
R
e
g
i
s
t
e
r
s
Address
D
Q
CLK
register
Output
Register
DQ [a:d]
17
17
CLK
CE0
CE1
CE2
A[16:0]
OE
CLK
CEN
Control
CLK
logic
Data
D
Q
CLK
Input
Register
32/36
OE
128K x 32/36
SRAM
Array
R/W
DQ [a:d
]
BWa
BWc
BWb
BWd
CLK
Q
D
FT
ADV / LD
LBO
Burst logic
addr. registers
Write delay
17
ZZ
CLK
17
17
32/36
32/36
32/36
32/36
32/36
Logic block diagram
Note: Pins 1,30,51,80 are NC for 32
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
LBO
A
A
A
A
A1
A0
NC
NC
V
SS
V
DD
NC
NC
A
A
A
A
A
A
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
A
A
CE0 CE1 BW
d
BW
c
BW
b
BW
a
CE2 V
DD
V
SS
CLK
R/
W
CEN OE ADV/LD NC NC A A
TQFP 14x20mm
A
DQPc, NC
DQc
DQc
V
DDQ
V
SSQ
DQc
DQc
DQc
DQc
V
SSQ
V
DDQ
DQc
DQc
FT
V
DD
V
DD
V
SS
DQd
DQd
V
DDQ
V
SSQ
DQd
DQd
DQd
DQd
V
SSQ
V
DDQ
DQd
DQd
DQPd, NC
DQPb, NC
DQb
DQb
V
DDQ
V
SSQ
DQb
DQb
DQb
DQb
V
SSQ
V
DDQ
DQb
DQb
V
SS
ZZ
DQa
DQa
V
DDQ
V
SSQ
DQa
DQa
DQa
DQa
V
SSQ
V
DDQ
DQa
DQa
DQPa, NC
V
DD
V
DD
Pin arrangement for TQFP (top view)
Selection Guide
-166
-133
-100
Units
Minimum cycle time
6
7.5
10
ns
Maximum pipelined clock frequency
166
133
100
MHz
Maximum pipelined clock access time
3.5
4
5
ns
Maximum operating current
475
425
325
mA
Maximum standby current
130
100
90
mA
Maximum CMOS standby current (DC)
30
30
30
mA
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Functional description
The AS7C33128NTD36A family is a high performance CMOS 4-Mbit synchronous Static Random Access Memory (SRAM) device organized as
131,072 words 32 or 36 bits that incorporates a LATE LATE Write.
This variation of the 4Mb sychronous SRAM uses the No Turnaround Delay (NTD) architecture, featuring an enhanced write operation that
improves bandwidth over pipelined burst devices. In a normal pipelined burst device, the write data, command, and address are all applied to
the device on the same clock edge. If a read command follows this write command, the system must wait for two dead cycles for valid data to
become available. These dead cycles can significantly reduce overall bandwidth for applications requiring random access or read-modify-write
operations.
NTD devices use the memory bus more efficiently by introducing a write latency that matches the two-cycle pipelined or one-cycle flow-
through read latency. Write data is applied two cycles after the write command and address, allowing the read pipeline to clear. With NTD,
write and read operations can be used in any order without producing dead bus cycles.
Assert R/W low to perform write cycles. Byte write enable controls write access to specific bytes, or can be tied low for full 32/36 bit writes.
Write enable signals, along with the write address, are registered on a rising edge of the clock. Write data is applied to the device two clock
cycles later. Unlike some asynchronous SRAMs, output enable OE does not need to be toggled for write operations. It can be tied low for
normal operations. Outputs go to a high impedance state when the device is deselected by any of the three chip enable inputs. (Refer to
synchronous truth table on page 4.) In pipelined mode, a two-cycle deselect latency allows pending read or write operations to be completed.
Use the ADV/LD (burst advance) input to perform burst read, write, and deselect operations. When ADV/LD is high, external addresses, chip
select, and R/W pins are ignored, and internal address counters increment in the count sequence specified by the LBO control. Any device
operations, including burst, can be stalled using the clock enable input, CEN = 1.
The AS7C33128NTD36A and AS7C33128NTD32A operate with a 3.3V 5% power supply for the device core (V
DD
). DQ circuits use a
separate power supply (V
DDQ
) that operates across 3.3V or 2.5V ranges. These devices are available in a 100-pin 1420 mm TQFP package.
Capacitance
Parameter
Symbol
Signals
Test conditions
Max
Unit
Input capacitance
C
IN
Address and control pins
V
in
= 0V
5
pF
I/O capacitance
C
I/O
I/O pins
V
in
= V
out
= 0V
7
pF
Burst order
Interleaved burst order
LBO = 1
Linear burst order
LBO = 0
Starting address
00
01
10
11
Starting address
00
01
10
11
First increment
01
00
11
10
First increment
01
00
11
10
Second increment
10
11
00
01
Second increment
10
11
00
01
Third increment
11
10
01
10
Third increment
11
10
01
10
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Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or
any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions may affect reliability.
Signal descriptions
Signal
I/O
Properties Description
CLK
I
CLOCK
Clock. All inputs except OE, FT, LBO, and ZZ are synchronous to this clock.
CEN
I
SYNC
Clock enable. When de-asserted high, the clock input signal is masked.
A, A0, A1
I
SYNC
Address. Sampled when all chip enables are active and ADV/LD is asserted.
DQ[a,b,c,d]
I/O
SYNC
Data. Driven as output when the chip is enabled and OE is active.
CE0, CE1,
CE2
I
SYNC
Synchronous chip enables. Sampled at the rising edge of CLK, when ADV/LD is asserted. Are
ignored when ADV/LD is high.
ADV/LD
I
SYNC
Advance or Load. When sampled high, the internal burst address counter will increment in
the order defined by the LBO input value. (refer to table on page 2) When low, a new address
is loaded.
R/W
I
SYNC
A high during LOAD initiates a READ operation. A low during LOAD initiates a WRITE
operation. Is ignored when ADV/LD is high.
BW[a,b,c,d]
I
SYNC
Byte write enables. Used to control write on individual bytes. Sampled along with WRITE
command and BURST WRITE.
OE
I
ASYNC
Asynchronous output enable. I/O pins are not driven when OE is inactive.
LBO
I
STATIC
Count mode. When driven high, count sequence follows Intel XOR convention. When
driven low, count sequence follows linear convention. This input should be static when the
device is in operation.
FT
I
STATIC
Flow-through mode.When low, enables single register flow-through mode. Connect to V
DD
if unused or for pipelined operation.
ZZ
I
ASYNC
Snooze. Places device in low power mode. Data is retained. Connect to VSS if unused.
NC
-
-
No connects. Note that pin 83 & 84 will be used for future address expansion to 8 Mb
and16Mb density.
Absolute maximum ratings
Parameter
Symbol
Min
Max
Unit
Power supply voltage relative to VSS
V
DD
, V
DDQ
0.5
+4.6
V
Input voltage relative to VSS (input pins)
V
IN
0.5
V
DD
+ 0.5
V
Input voltage relative to VSS (I/O pins)
V
IN
0.5
V
DDQ
+ 0.5
V
Power dissipation
P
D
1.8
W
DC output current
I
OUT
50
mA
Storage temperature (plastic)
T
stg
65
+150
o
C
Temperature under bias (Junction)
T
bias
65 +135
o
C
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Key: X = don't care, L = low, H = high.
1. Should be low for burst write, unless specific bytes need to be inhibited.
2. Refer to state diagram below.
Synchronous truth table
CE0
CE1
CE2
ADV/
LD
R/W BW[a:d]
OE
CEN
Address source
CLK
Operation
H
X
X
L
X
X
X
L
NA
L to H
Deselect, high-Z
X
L
X
L
X
X
X
L
NA
L to H
Deselect, high-Z
X
X
H
L
X
X
X
L
NA
L to H
Deselect, high-Z
L
H
L
L
H
X
X
L
External
L to H
Begin read
L
H
L
L
L
L
X
L
External
L to H
Begin write
X
X
X
H
X
X
1
X
L
Burst counter
L to H
Burst
2
X
X
X
X
X
X
X
H
Stall
L to H
Inhibit the CLK
TQFP thermal resistance
Description
Conditions
Symbol
Typical
Units
Thermal resistance
(Junction to Ambient)
1
7KLV SDUDPHWHU LV VDPSOHG
Test conditions follow standard test methods and
procedures for measuring thermal impedance, per
EIA/JESD51.
JA
40
C/W
Thermal resistance
(Junction to Top of Case)
1
JC
8
C/W
Dsel
Dsel
Re
ad
Read
Burst
Burst
Write
Read
Write
Burst
Read
Read
Wr
ite
Dsel
Read
Burst
Write
Dsel
Dse
l
Wr
ite
W
rit
e
Burst
Dsel
Burst
Burst
Write
Read
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Recommended operating conditions
Parameter
Symbol
Min
Nominal
Max
Unit
Supply voltage
V
DD
3.135
3.3
3.465
V
VSS
0.0
0.0
0.0
V
3.3V I/O supply
voltage
V
DDQ
3.135
3.3
3.465
V
VSSQ
0.0
0.0
0.0
2.5V I/O supply
voltage
V
DDQ
2.35
2.5
2.65
V
VSSQ
0.0
0.0
0.0
Input voltages
1
1 Input voltage ranges apply to 3.3V I/O operation. For 2.5V operation, contact factory for input specifications.
Address and
control pins
V
IH
2.0
V
DD
+ 0.3
V
V
IL
0.5
2
2 V
IL
min. = 2.0V for pulse width less than 0.2 x t
RC
.
0.8
V
I/O pins
V
IH
2.0
V
DDQ
+ 0.3
V
V
IL
-0.5
2
0.8
Ambient operating temperature
T
A
0
70
C
DC electrical characteristics for 3.3V I/O operation
Parameter
Sym
Test conditions
166
133
100
Unit
Min
Max
Min
Max
Min
Max
Input leakage current
1
1 LBO pin has an internal pull-up, and input leakage = 10
A.
Note: ICC given with no output loading. ICC increases with faster cycle times and greater output loading.
|
I
LI
|
V
DD
= Max, V
in
= VSS to V
DD
2
2
2
A
Output leakage
current
|
I
LO
|
OE
V
IH,
V
DD
= Max,
V
out
= VSS to V
DD
2
2
2
A
Operating power supply
current
I
CC
CE = V
IL
, CE = V
IH
, CE = V
IL
,
f = f
max,
I
out
= 0 mA
475
425
325
mA
Standby power supply
current
I
SB
Deselected, f = f
max
130
100
90
mA
I
SB1
Deselected, f = 0,
all V
IN
0.2V or
V
DD
- 0.2V
30
30
30
mA
I
SB2
Deselected, f=f
Max
, ZZ
V
DD
-
0.2V All V
IN
V
IL
or
V
IH
30
30
30
mA
Output voltage
V
OL
I
OL
= 8 mA, V
DDQ
= 3.6V
0.4
0.4
0.4
V
V
OH
I
OH
= 4 mA, V
DDQ
= 3.0V
2.4
2.4
2.4
V
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See "Notes" on page 9.
DC electrical characteristics for 2.5V I/O operation
Parameter
Sym
Test conditions
166
133
100
Unit
Min
Max
Min
Max
Min
Max
Output leakage
current
|
I
LO
|
OE
V
IH,
V
DD
= Max,
V
out
= VSS to V
DD
-1
1
-1
1
-1
1
A
Output voltage
V
OL
I
OL
= 2 mA, V
DDQ
= 2.65V
0.7
0.7
0.7
V
V
OH
I
OH
= 2 mA, V
DDQ
= 2.35V
1.7
1.7
1.7
Timing characteristics over operating range
Parameter
Sym
166
133
100
Unit
Notes
Min
Max
Min
Max
Min
Max
Clock frequency
F
MAX
-
166
-
133
-
100
MHz
Cycle time (pipelined mode)
t
CYC
6
-
7.5
-
10
-
ns
Cycle time (flow-through mode)
t
CYCF
10
-
12
-
12
-
ns
Clock access time (pipelined mode)
t
CD
-
3.5
-
4.0
-
5.0
ns
Clock access time (flow-through
mode)
t
CDF
-
9
-
10
-
12
ns
Output enable low to data valid
t
OE
-
3.5
-
4.0
-
5.0
ns
Clock high to output low Z
t
LZC
0
-
0
-
0
-
ns
2,3,4
Data output invalid from clock high
t
OH
1.5
-
1.5
-
1.5
-
ns
4
Output enable low to output low Z
t
LZOE
0
-
0
-
0
-
ns
2,3,4
Output enable high to output high Z
t
HZOE
-
3.5
-
4.0
-
4.5
ns
2,3,4
Clock high to output high Z
t
HZC
-
3.5
-
4.0
-
4.5
ns
2,3,4
Clock high to output high Z
t
HZCN
-
1.5
-
2.0
-
2.5
ns
5
Clock high pulse width
t
CH
2.4
-
2.5
-
3.0
-
ns
6
Clock low pulse width
t
CL
2.2
-
2.5
-
3.0
-
ns
6
Address setup to clock high
t
AS
1.5
-
1.5
-
2.0
-
ns
7
Data setup to clock high
t
DS
1.5
-
1.5
-
2.0
-
ns
7
Write setup to clock high
t
WS
1.5
-
1.5
-
2.0
-
ns
7
Chip select setup to clock high
t
CSS
1.5
-
1.5
-
2.0
-
ns
7
Clock enable setup to clock high
t
CENS
1.5
-
1.5
-
2.0
-
ns
7
ADV/LD
setup to clock high
t
ADVS
1.5
-
1.5
-
2.0
-
ns
7
Address hold from clock high
t
AH
0.5
-
0.5
-
0.5
-
ns
7
Data hold from clock high
t
DH
0.5
-
0.5
-
0.5
-
ns
7
Write hold from clock high
t
WH
0.5
-
0.5
-
0.5
-
ns
7
ADV/LD
hold from clock high
t
ADVH
0.5
-
0.5
-
0.5
-
ns
7
Clock enable hold from clock high
t
CENH
0.5
-
0.5
-
0.5
-
ns
7
Output rise time (0 pF load)
t
R
1.5
-
1.5
-
1.5
-
V/ns
Output fall time (0 pF load)
t
F
1.5
-
1.5
-
1.5
-
V/ns
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Timing waveform of read/write cycle
Note: = XOR when LBO = high/no connect. = ADD when LBO = low.
BW[a:b] is don't care.
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BURST
WRITE
D(A2 1)
READ
Q(A3)
READ
Q(A4)
BURST
READ
Q(A4
1)
WRITE
D(A5)
READ
Q(A6)
WRITE
D(A7)
DSEL
WRITE
D(A1)
WRITE
D(A2)
W
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Notes: OE is low.
= XOR when LBO = high/no connect. = ADD when LBO = low
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BURST
Q(A1 01)
STALL
DSEL
BURST
DSEL
WRITE
D(A2)
BURST
NOP
D(A2 01)
WRITE
NOP
D(A3)
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Q(A1 10)
BURST
D(A2 10)
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AC test conditions
Z
0
=50
D
out
50
V
L
=1.5V
Figure B: Output load (A)
30 pF*
Figure A: Input waveform
10%
90%
VSS
90%
10%
+3.0V
Output Load: For
t
LZC
, t
LZOE
, t
HZOE
, t
HZC,
see Figure C. For all others, see Figure B.
Input pulse level: VSS to 3V. See Figure A.
Input rise and fall time (measured at 0.3V and 2.7V): 2 ns. See Figure A.
Input and output timing reference levels: 1.5V.
353
/ 1538
5 pF*
319
/ 1667
D
OUT
GND
Figure C: Output load (B)
*including scope
and jig capacitance
Thevenin equivalent:
+3.3V for 3.3V I/O,
+2.5V for 2.5V I/O
Notes
Package dimensions
100-pin quad flat pack (TQFP)
TQFP
Min
Max
A1
0.05
0.15
A2
1.35
1.45
b
0.22
0.38
c
0.09
0.20
D
13.90
14.10
E
19.90
20.10
e
0.65 nominal
Hd
15.90
16.10
He
21.90
22.10
L
0.45
0.75
L1
1.00 nominal
0
7
Dimensions in millimeters
He
E
Hd
D
b
e
A1 A2
L1
L
c
1
For test conditions, see AC Test Conditions, Figures A, B, and C.
2
This parameter measured with output load condition in Figure C
3
This parameter is sampled and not 100% tested.
4
t
HZOE
is less than t
LZOE
, and t
HZC
is less than t
LZC
at any given temperature
and voltage.
5
t
HZCN
is a
no-load parameter to indicate exactly when SRAM outputs
have stopped driving.
6
t
CH
measured as high above VIH, and t
CL
measured as low below VIL
7
This is a synchronous device. All addresses must meet the specified setup
and hold times for all rising edges of CLK. All other synchronous inputs
must meet the setup and hold times with stable logic levels for all rising
edges of CLK when chip is enabled.
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AS7C33128NTD32A
AS7C33128NTD36A
Y
$OOLDQFH 6HPLFRQGXFWRU
3 RI
1.Alliance Semiconductor SRAM prefix
2.Operating voltage: 33 = 3.3V
3.Organization: 128 = 128K
4.NTD
= No Turnaround Delay
5.Organization: 32 = x32, 36 = x36
6.Production version: A = first production version
7.Clock speed (MHz)
8.Package type: TQ = TQFP
9.Operating temperature: C = commercial ( 0
C to 70
C), I = industrial (-40
C to 85
C)
Ordering information
Package
Width
166 MHz
133 MHz
100 MHz
TQFP
32
AS7C33128NTD32A-166TQC
AS7C33128NTD32A-133TQC
AS7C33128NTD32A-100TQC
TQFP
36
AS7C33128NTD36A-166TQC
AS7C33128NTD36A-133TQC
AS7C33128NTD36A-100TQC
FBGA
32
AS7C33128NTD32A-166BC
AS7C33128NTD32A-133BC
AS7C33128NTD32A-100BC
FBGA
36
AS7C33128NTD36A-166BC
AS7C33128NTD36A-133BC
AS7C33128NTD36A-100BC
Part numbering guide
AS7C
33
128
NTD
32/36
A
XXX
TQ
C/I
1
2
3
4
5
6
7
8
9
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