AS7C33512NTD32-36A.V032003.fm

March 2003
Advance Information

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AS7C33512NTD32A
AS7C33512NTD36A

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Features

· Organization: 524,288 words × 32 or 36 bits
· NTD

TM1

architecture for efficient bus operation

· Fast clock speeds to 200 MHz in LVTTL/LVCMOS
· Fast clock to data access: 3/3.4/3.8 ns
· Fast OE access time:

3/3.4/3.8 ns

· Fully synchronous operation
· Flow-through or pipelined mode
· Asynchronous output enable control

1. NTD

is a trademark of Alliance Semiconductor Corporation.

· Available in 100-pin TQFP and 165-ball BGA package
· Byte write enables
· Clock enable for operation hold
· Multiple chip enables for easy expansion
· 3.3V core power supply
· 2.5V or 3.3V I/O operation with separate V

DDQ

· Self-timed write cycles
· Interleaved or linear burst modes
· Snooze mode for standby operation

Logic block diagram

Selection guide

-200

-166

-133

Units

Minimum cycle time

7.5

Maximum pipelined clock frequency

200

166

133

MHz

Maximum pipelined clock access time

3.0

3.4

3.8

Maximum operating current

400

350

325

Maximum standby current

130

120

110

Maximum CMOS standby current (DC)

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Pin and ball assignment

165-ball BGA - top view

100-pin TQFP - top view

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1 A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired.

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Functional description

The AS7C33512NTD32A/36A family is a high performance CMOS 16 Mbit synchronous Static Random Access Memory (SRAM) organized as
524,288 words × 32 or 36 bits and incorporates a LATE LATE Write.

This variation of the 16Mb+ synchronous SRAM uses the No Turnaround Delay (NTD

) architecture, featuring an enhanced write operation

that improves bandwidth over pipelined burst devices. In a normal pipelined burst device, the write data, command, and address are all applied
to the device on the same clock edge. If a read command follows this write command, the system must wait for two 'dead' cycles for valid data
to become available. These dead cycles can significantly reduce overall bandwidth for applications requiring random access or read-modify-
write operations.

NTD

devices use the memory bus more efficiently by introducing a write latency which matches the two-cycle pipelined or one-cycle flow-

through read latency. Write data is applied two cycles after the write command and address, allowing the read pipeline to clear. With NTD

write and read operations can be used in any order without producing dead bus cycles.

Assert R/W low to perform write cycles. Byte write enable controls write access to specific bytes, or can be tied low for full 18 bit writes. Write
enable signals, along with the write address, are registered on a rising edge of the clock. Write data is applied to the device two clock cycles
later. Unlike some asynchronous SRAMs, output enable OE does not need to be toggled for write operations; it can be tied low for normal
operations. Outputs go to a high impedance state when the device is de-selected by any of the three chip enable inputs. In pipelined mode, a
two cycle deselect latency allows pending read or write operations to be completed.

Use the ADV (burst advance) input to perform burst read, write and deselect operations. When ADV is high, external addresses, chip select, R/W pins
are ignored, and internal address counters increment in the count sequence specified by the LBO control. Any device operations, including burst, can
be stalled using the CEN=1, the clock enable input.

The AS7C33512NTD32A/36A operates with a 3.3V ± 5% power supply for the device core (V

). DQ circuits use a separate power supply

DDQ

) that operates across 3.3V or 2.5V ranges. These devices are available in a 100-pin TQFP package and 165 BGA Ball Grid Array package.

Capacitance

Burst order

Parameter

Symbol

Signals

Test conditions

Max

Unit

Input capacitance

Address and control pins

= 0V

I/O capacitance

I/O

I/O pins

= V

out

= 0V

Interleaved burst order LBO = 1

Linear burst order LBO = 0

A1 A0

Starting address

0 0

0 1

1 0

1 1

Starting Address

0 0

0 1

1 0

1 1

First increment

0 1

0 0

1 1

1 0

First increment

0 1

1 0

1 1

0 0

Second increment

1 0

1 1

0 0

0 1

Second increment

1 0

1 1

0 0

0 1

Third increment

1 1

1 0

0 1

0 0

Third increment

1 1

0 0

0 1

1 0

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Signal descriptions

Absolute maximum ratings

Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only, and functional operation of
the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions may affect reliability.

Signal

I/O

Properties Description

CLK

CLOCK

Clock. All inputs except OE, FT, LBO, and ZZ are synchronous to this clock.

CEN

SYNC

Clock enable. When de-asserted high, the clock input signal is masked.

A, A0, A1

SYNC

Address. Sampled when all chip enables are active and ADV/LD is asserted.

DQ[a,b,c,d]

I/O

SYNC

Data. Driven as output when the chip is enabled and OE is active.

CE0, CE1,
CE2

SYNC

Synchronous chip enables. Sampled at the rising edge of CLK, when ADV/LD is asserted. Are
ignored when ADV/LD is high.

ADV/LD

SYNC

Advance or Load. When sampled high, the internal burst address counter will increment in
the order defined by the LBO input value. (refer to table on page 2) When low, a new
address is loaded.

R/W

SYNC

A high during LOAD initiates a READ operation. A low during LOAD initiates a WRITE
operation. Is ignored when ADV/LD is high.

BW[a,b,c,d]

SYNC

Byte write enables. Used to control write on individual bytes. Sampled along with WRITE
command and BURST WRITE.

ASYNC

Asynchronous output enable. I/O pins are not driven when OE is inactive.

LBO

STATIC

Count mode. When driven high, count sequence follows Intel XOR convention. When
driven low, count sequence follows linear convention. This input should be static when the
device is in operation.

STATIC

Flow-through mode.When low, enables single register flow-through mode. Connect to V

if unused or for pipelined operation.

TDO

SYNC

Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK. (BGA only)

TDI

SYNC

Serial data-in to the JTAG circuit. Sampled on the rising edge of TCK. (BGA only)

TMS

SYNC

This pin controls the Test Access Port state machine. Sampled on the rising edge of TCK.
(BGA only)

TCK

SYNC

Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK. (BGA only)

ASYNC

Snooze. Places device in low power mode; data is retained. Connect to GND if unused.

No connects.

Parameter

Symbol

Min

Max

Unit

Power supply voltage relative to GND

, V

DDQ

0.5

+4.6

Input voltage relative to GND (input pins)

0.5

+ 0.5

Input voltage relative to GND (I/O pins)

0.5

DDQ

+ 0.5

Power dissipation

1.8

DC output current

OUT

Storage temperature (plastic)

stg

+150

Temperature under bias (junction)

bias

65 +150

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Synchronous truth table

Key: X = don't care, L = low, H = high

State diagram for NTD SRAM

Recommended operating conditions

CE0

CE1

CE2

ADV/LD

R/W

BW[a,b]

CEN

Address source

CLK

Operation

L to H

Deselect, high-Z

L to H

Deselect, high-Z

L to H

Deselect, high-Z

External

L to H

Begin read

External

L to H

Begin write

1 Should be low for burst write, unless specific bytes need to be inhibited

Burst counter

L to H

Burst

2 Refer to state diagram below.

Stall

L to H

Inhibit the CLK

Parameter

Symbol

Min

Nominal

Max

Unit

Supply voltage

3.135

3.3

3.465

GND

0.0

3.3V I/O supply voltage

DDQ

2.375

3.3

3.465

GND

0.0

2.5V I/O supply voltage

DDQ

2.35

2.5

2.65

GND

0.0

Input voltages

1 Input voltage ranges apply to 3.3V I/O operation. For 2.5V operation, contact factory for input specifications.

Address and
control pins

2.0

+ 0.3

0.5

2 V

min = 2.0V for pulse width less than 0.2 x t

0.7

I/O pins

2.0

DDQ

+ 0.3

-0.5

0.7

Ambient operating temperature

° C

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Document Outline

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