December 2004

AS7C3364PFS32B

AS7C3364PFS36B

3.3V 64K X 32/36 pipeline burst synchronous SRAM

12/10/04; v.1.4

Alliance Semiconductor

P. 1 of 19

Features

· Organization: 65,536 words × 32 or 36 bits
· Fast clock speeds to 200 MHz
· Fast clock to data access: 3.0/3.5/4.0 ns
· Fast OE access time: 3.0/3.5/4.0 ns
· Fully synchronous register-to-register operation
· Single-cycle deselect
· Asynchronous output enable control
· Available in 100-pin TQFP package

· Linear or interleaved burst control
· Individual byte write and global write
· Snooze mode for reduced power-standby
· Common data inputs and data outputs
· Multiple chip enables for easy expansion
· 3.3V core power supply
· 2.5V or 3.3V I/O operation with separate V

DDQ

Logic block diagram

64K × 32/36

Memory

array

Burst logic

CLK

CLR

Address

CE
CLK

CLK

Byte write

registers

CLK

Byte write

registers

CLK

Byte write

registers

CLK

Byte write

registers

Enable

CLK

Enable

CLK

delay

Output

registers

Input

registers

Power

down

36/32

GWE

BWE

ADV

ADSC

ADSP

CLK

CE0

CE1

CE2

A[15:0]

LBO

CLK

36/32

DQ [a:d]

Selection guide

200

166

133

Units

Minimum cycle time

7.5

Maximum clock frequency

200

166

133

MHz

Maximum clock access time

3.0

3.5

Maximum operating current

375

350

325

Maximum standby current

130

100

Maximum CMOS standby current (DC)

AS7C3364PFS32B

AS7C3364PFS36B

12/10/04; v.1.4

Alliance Semiconductor

P. 2 of 19

2 Mb Synchronous SRAM products list

1,2

1 Core Power Supply: VDD = 3.3V + 0.165V
2 I/O Supply Voltage: VDDQ = 3.3V + 0.165V for 3.3V I/O

VDDQ = 2.5V + 0.125V for 2.5V I/O

PL-SCD

Pipelined Burst Synchronous SRAM - Single Cycle Deselect

PL-DCD

Pipelined Burst Synchronous SRAM - Double Cycle Deselect

Flow-through Burst Synchronous SRAM

Org

Part Number

Mode

Speed

128KX18

AS7C33128PFS18B

PL-SCD

200/166/133 MHz

64KX32

AS7C3364PFS32B

PL-SCD

200/166/133 MHz

64KX36

AS7C3364PFS36B

PL-SCD

200/166/133 MHz

128KX18

AS7C33128PFD18B

PL-DCD

200/166/133 MHz

64KX32

AS7C3364PFD32B

PL-DCD

200/166/133 MHz

64KX36

AS7C3364PFD36B

PL-DCD

200/166/133 MHz

128KX18

AS7C33128FT18B

6.5/7.5/8.0/10 ns

64KX32

AS7C3364FT32B

6.5/7.5/8.0/10 ns

64KX36

AS7C3364FT36B

6.5/7.5/8.0/10 ns

AS7C3364PFS32B

AS7C3364PFS36B

12/10/04; v.1.4

Alliance Semiconductor

P. 3 of 19

Pin arrangement

DQP

/NC

DDQ

SSQ

DDQ

SSQ

DDQ

DQP

/NC

DQP

/NC

DDQ

SSQ

DDQ

SSQ

DDQ

DQP

/NC

LBO

A A A A A1 A0 NC NC

NC NC

A A A A A A

31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81

A A CE

GWE BWE OE ADSC ADSP ADV A A

VDD

TQFP 14 × 20 mm

Note: Pins 1,30,51,80 are NC for X32

AS7C3364PFS32B

AS7C3364PFS36B

12/10/04; v.1.4

Alliance Semiconductor

P. 4 of 19

Functional description

The AS7C3364PFS32B and AS7C3364PFS36B are high-performance CMOS 2-Mbit synchronous Static Random Access
Memory (SRAM) devices organized as 65,536 words × 32 or 36 bits, and incorporate a two-stage register-register pipeline for
highest frequency on any given technology.

Timing for these devices is compatible with existing Pentium

synchronous cache specifications. This architecture is suited

for ASIC, DSP and PowerPC

TM1

-based systems in computing, datacom, instrumentation, and telecommunications systems.

Fast cycle times of 5.0/6.0/7.5 ns with clock access times (t

) of 3.0/3.5/4.0 ns enable 200, 166 and 133 MHz bus

frequencies. Three chip enable (CE) inputs permit easy memory expansion. Burst operation is initiated in one of two ways: the
controller address strobe (ADSC), or the processor address strobe (ADSP). The burst advance pin (ADV) allows subsequent
internally generated burst addresses.

Read cycles are initiated with ADSP (regardless of WE and ADSC) using the new external address clocked into the on-chip
address register when ADSP is sampled Low, the chip enables are sampled active, and the output buffer is enabled with OE. In
a read operation the data accessed by the current address, registered in the address registers by the positive edge of CLK, are
carried to the data-out registers and driven on the output pins on the next positive edge of CLK. ADV is ignored on the clock
edge that samples ADSP asserted, but is sampled on all subsequent clock edges. Address is incremented internally for the next
access of the burst when ADV is sampled Low, and both address strobes are High. Burst mode is selectable with the LBO
input. With LBO unconnected or driven High, burst operations use a Pentium

count sequence. With LBO driven LOW, the

device uses a linear count sequence suitable for PowerPC

and many other applications.

Write cycles are performed by disabling the output buffers with OE and asserting a write command. A global write enable
GWE writes all 32/36 bits regardless of the state of individual BW[a:d] inputs. Alternately, when GWE is High, one or more
bytes may be written by asserting BWE and the appropriate individual byte BWn signal(s).

BWn is ignored on the clock edge that samples ADSP Low, but is sampled on all subsequent clock edges. Output buffers are
disabled when BWn is sampled LOW (regardless of OE). Data is clocked into the data input register when BWn is sampled
Low. Address is incremented internally to the next burst address if BWn and ADV are sampled Low.

Read or write cycles may also be initiated with ADSC instead of ADSP. The differences between cycles initiated with ADSC
and ADSP are as follows:

· ADSP must be sampled HIGH when ADSC is sampled LOW to initiate a cycle with ADSC.
· WE signals are sampled on the clock edge that samples ADSC LOW (and ADSP High).
· Master chip enable CE0 blocks ADSP, but not ADSC.

AS7C3364PFS32B and AS7C3364PFS36B family operates from a core 3.3V power supply. I/Os use a separate power supply
that can operate at 2.5V or 3.3V. These devices are available in a 100-pin 14 × 20 mm TQFP package.

TQFP capacitance

* Guaranteed not tested

TQFP thermal resistance

1 PowerPC

is a trademark International Business Machines Corporation.

Parameter

Symbol

Test conditions

Min

Max

Unit

Input capacitance

= 0V

I/O capacitance

I/O

OUT

= 0V

Description

Conditions

Symbol

Typical

Units

Thermal resistance
(junction to ambient)

1 This parameter is sampled

Test conditions follow standard test methods and

procedures for measuring thermal impedance,

per EIA/JESD51

1layer

°C/W

4layer

°C/W

Thermal resistance
(junction to top of case)

°C/W

AS7C3364PFS32B

AS7C3364PFS36B

12/10/04; v.1.4

Alliance Semiconductor

P. 5 of 19

Snooze Mode

SNOOZE MODE is a low current, power-down mode in which the device is deselected and current is reduced to I

SB2

. The duration of

SNOOZE MODE is dictated by the length of time the ZZ is in a High state.

The ZZ pin is an asynchronous, active high input that causes the device to enter SNOOZE MODE.

When the ZZ pin becomes a logic High, I

SB2

is guaranteed after the time t

ZZI

is met. After entering SNOOZE MODE, all inputs except ZZ is

disabled and all outputs go to High-Z. Any operation pending when entering SNOOZE MODE is not guaranteed to successfully complete.
Therefore, SNOOZE MODE (READ or WRITE) must not be initiated until valid pending operations are completed. Similarly, when exiting
SNOOZE MODE during t

PUS

, only a DESELECT or READ cycle should be given while the SRAM is transitioning out of SNOOZE

MODE.

Signal descriptions

Signal

I/O

Properties

Description

CLK

CLOCK

Clock. All inputs except OE, ZZ, LBO are synchronous to this clock.

A,A0,A1

SYNC

Address. Sampled when all chip enables are active and ADSC or ADSP are asserted.

DQ[a,b,c,d]

I/O

SYNC

Data. Driven as output when the chip is enabled and OE is active.

CE0

SYNC

Master chip enable. Sampled on clock edges when ADSP or ADSC is active. When CE0
is inactive, ADSP is blocked. Refer to the Synchronous Truth Table for more information.

CE1, CE2

SYNC

Synchronous chip enables. Active HIGH and active Low, respectively. Sampled on clock
edges when ADSC is active or when CE0 and ADSP are active.

ADSP

SYNC

Address strobe processor. Asserted LOW to load a new bus address or to enter standby
mode.

ADSC

SYNC

Address strobe controller. Asserted LOW to load a new address or to enter standby mode.

ADV

SYNC

Advance. Asserted LOW to continue burst read/write.

GWE

SYNC

Global write enable. Asserted LOW to write all 32/36 bits. When High, BWE and
BW[a:d] control write enable.

BWE

SYNC

Byte write enable. Asserted LOW with GWE = HIGH to enable effect of BW[a:d] inputs.

BW[a,b,c,d]

SYNC

Write enables. Used to control write of individual bytes when GWE = HIGH and BWE =
Low. If any of BW[a:d] is active with GWE = HIGH and BWE = LOW the cycle is a
write cycle. If all BW[a:d] are inactive the cycle is a read cycle.

ASYNC

Asynchronous output enable. I/O pins are driven when OE is active and the chip is in read
mode.

LBO

STATIC

Selects Burst mode. When tied to V

or left floating, device follows Interleaved Burst

order. When driven Low, device follows linear Burst order. This signal is internally
pulled High.

ASYNC

Snooze. Places device in low power mode; data is retained. Connect to GND if unused.

No connect

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Document Outline

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: AS7C3364PFS32B-166TQCN

Document Outline

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: AS7C3364PFS32B-166TQCN