March 2002
Copyright Alliance Semiconductor. All rights reserved.
AS7C4098
AS7C34098
5V/3.3V 256K 16 CMOS SRAM
5/23/02; v.1.8
Alliance Semiconductor
P. 1 of 12
Features
AS7C4098 (5V version)
AS7C34098 (3.3V version)
Industrial and commercial temperature
Organization: 262,144 words 16 bits
Center power and ground pins
High speed
- 10/12/15/20 ns address access time
- 5/6/7/8 ns output enable access time
Low power consumption: ACTIVE
- 1375 mW (AS7C4098)/max @ 12 ns
- 468 mW (AS7C34098)/max @ 12 ns
Low power consumption: STANDBY
- 110 mW (AS7C4098)/max CMOS
- 72 mW (AS7C34098)/max CMOS
Individual byte read/write controls
Easy memory expansion with CE, OE inputs
TTL- and CMOS-compatible, three-state I/O
44-pin JEDEC standard packages
- 400-mil SOJ
- TSOP 2
- 48-ball FBGA 7 x 11 mm
ESD protection
2000 volts
Latch-up current
200 mA
Logic block diagram
1024 256 16
Array
(4,194,304)
OE
CE
WE
Column decoder
Ro
w Decoder
A0
A1
A2
A3
A4
A6
A7
A8
V
CC
GND
A12
A5
A9
A1
0
A1
1
A1
4
A1
5
A1
6
A1
7
A13
Control circuit
I/O1I/O8
I/O9I/O16
UB
LB
I/O
buffer
Pin arrangement for SOJ and TSOP 2
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
I/O14
I/O13
GND
V
CC
I/O12
I/O11
I/O10
I/O9
NC
A14
A13
A12
A11
A10
A4
CE
I/O1
I/O2
I/O3
I/O4
V
CC
GND
I/O5
I/O6
I/O7
I/O8
WE
A5
A6
A7
TSOP2
21
22
A8
A9
UB
LB
I/O16
I/O15
2
A1
3
A2
4
A3
1
A0
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
43
42
41
44
A16
A15
OE
A17
44-pin (400 mil) SOJ
Selection guide
10
12
15
20
Unit
Maximum address access time
10
12
15
20
ns
Maximum output enable access time
5
6
7
9
ns
Maximum operating current
AS7C4098
250
220
180
mA
AS7C34098
160
130
110
100
mA
Maximum CMOS standby current
AS7C4098
20
20
20
mA
AS7C34098
20
20
20
20
mA
AS7C4098
AS7C34098
5/23/02; v.1.8
Alliance Semiconductor
P. 3 of 12
Functional description
The AS7C4098 and AS7C34098 are high-performance CMOS 4,194,304-bit Static Random Access Memory (SRAM) devices
organized as 262,144 words 16 bits. They are designed for memory applications where fast data access, low power, and
simple interfacing are desired.
Equal address access and cycle times (t
AA
, t
RC
, t
WC
) of 10/12/15/20 ns with output enable access times (t
OE
) of 5/6/7/8 ns are
ideal for high-performance applications. The chip enable input CE permits easy memory expansion with multiple-bank memory
systems.
When CE is High the device enters standby mode. The standard AS7C4098 is guaranteed not to exceed 110 mW power
consumption in CMOS standby mode. A write cycle is accomplished by asserting write enable (WE) and chip enable (CE). Data
on the input pins I/O1I/O16 is written on the rising edge of WE (write cycle 1) or CE (write cycle 2). To avoid bus contention,
external devices should drive I/O pins only after outputs have been disabled with output enable (OE) or write enable (WE).
A read cycle is accomplished by asserting output enable (OE) and chip enable (CE), with write enable (WE) High. The chip
drives I/O pins with the data word referenced by the input address. When either chip enable or output enable is inactive, or
write enable is active, output drivers stay in high-impedance mode.
These devices provide multiple center power and ground pins, and separate byte enable controls, allowing individual bytes to be
written and read. LB controls the lower bits, I/O1I/O8, and UB controls the higher bits, I/O9I/O16.
All chip inputs and outputs are TTL- and CMOS-compatible, and operation is from either a single 5V (AS7C4098) or 3.3V
(AS7C34098) supply. Both devices are available in the JEDEC standard 400-mL, 44-pin SOJ, TSOP 2, and 48 - CSP/BGA
packages.
Note: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect reliability.
Absolute maximum ratings
Parameter
Device
Symbol
Min
Max
Unit
Voltage on V
CC
relative to GND
AS7C4098
V
t1
0.50
+7.0
V
AS7C34098
V
t1
0.50
+5.0
V
Voltage on any pin relative to GND
V
t2
0.50
V
CC
+0.50
V
Power dissipation
P
D
1.5
W
Storage temperature (plastic)
T
stg
65
+150
C
Ambient temperature with V
CC
applied
T
bias
55 +125
C
DC current into outputs (low)
I
OUT
20
mA
Truth table
CE
WE
OE
LB
UB
I/O1I/O8
I/O9I/O16
Mode
H
X
X
X
X
High Z
High Z
Standby (I
SB
, I
SB1
)
L
H
H
X
X
High Z
High Z
Output disable (I
CC
)
L
X
X
H
H
L
H
L
L
H
D
OUT
High Z
Read (I
CC
)
H
L
High Z
D
OUT
L
L
D
OUT
D
OUT
L
L
X
L
H
D
IN
High Z
Write (I
CC
)
H
L
High Z
D
IN
L
L
D
IN
D
IN
Key: X = Don't care, L = Low, H = High.
AS7C4098
AS7C34098
5/23/02; v.1.8
Alliance Semiconductor
P. 4 of 12
Recommended operating conditions
Parameter
Symbol
Min
Typical
Max
Unit
Supply voltage
AS7C4098
V
CC
(12/15/20)
4.5
5.0
5.5
V
AS7C34098
V
CC
(10)
3.15
3.3
3.6
V
AS7C34098
V
CC
(12/15/20)
3.0
3.3
3.6
V
Input voltage
AS7C4098
V
IH
2.2
V
CC
+ 0.5
V
AS7C34098
V
IH
2.0
V
CC
+ 0.5
V
V
IL
0.5
1
1 V
IL
min = 3.0V for pulse width less than t
RC
/2.
0.8
V
Ambient operating temperature
commercial
T
A
0
70
C
industrial
T
A
40
85
C
DC operating characteristics (over the operating range)
Parameter
Symbol
Test conditions
10
12
15
20
Unit
Min Max Min Max Min Max Min Max
Input leakage
current
|I
LI
|
V
CC
= Max
V
IN
= GND to V
CC
1
1
1
1
A
Output leakage
current
|I
LO
|
V
CC
= Max
CE = V
IH
or OE = V
IH
or WE = V
IL
V
I/O
= GND to V
CC
1
1
1
1
A
Operating
power supply
current
I
CC
V
CC
= Max
Min cycle, 100% duty
CE = V
IL
, I
OUT
= 0mA
AS7C4098
250
220
180
mA
AS7C34098
160
130
110
100
mA
Standby power
supply current
I
SB
V
CC
= Max
CE = V
IH
, f = Max
AS7C4098
60
60
60
mA
AS7C34098
60
60
60
60
mA
I
SB1
V
CC
= Max
CE
V
CC
0.2V, V
IN
V
CC
0.2V or V
IN
0.2V, f = 0
AS7C4098
20
20
20
mA
AS7C34098
20
20
20
20
mA
Output voltage
V
OL
I
OL
= 8 mA, V
CC
= Min
0.4
0.4
0.4
0.4
V
V
OH
I
OH
= 4 mA, V
CC
= Min
2.4
2.4
2.4
2.4
V
Capacitance (f = 1MHz, T
a
= 25
C, V
CC
= NOMINAL)
Parameter
Symbol
Signals
Test conditions
Max
Unit
Input capacitance
C
IN
A, CE, WE, OE, UB, LB
V
IN
= 0V
6
pF
I/O capacitance
C
I/O
I/O
V
IN
= V
OUT
= 0V
8
pF
AS7C4098
AS7C34098
5/23/02; v.1.8
Alliance Semiconductor
P. 5 of 12
Key to switching waveforms
Read waveform 1 (address controlled)
Read cycle (over the operating range)
Parameter
Symbol
10
12
15
20
Unit Notes
Min
Max
Min
Max
Min
Max
Min
Max
Read cycle time
t
RC
10
12
15
20
ns
Address access time
t
AA
10
12
15
20
ns
Chip enable (CE) access time
t
ACE
10
12
15
20
ns
Output enable (OE) access time
t
OE
5
6
7
8
ns
Output hold from address change
t
OH
3
3
3
3
ns
5
CE Low to output in low Z
t
CLZ
0
3
0
0
ns
4, 5
CE High to output in higfch Z
t
CHZ
5
6
7
9
ns
4, 5
OE Low to output in low Z
t
OLZ
0
0
0
0
ns
4, 5
OE High to output in high Z
t
OHZ
5
6
7
9
ns
4, 5
LB, UB access time
t
BA
5
6
7
8
ns
LB, UB Low to output in low Z
t
BLZ
0
0
0
0
ns
LB, UB High to output in high Z
t
BHZ
5
6
7
9
ns
Power up time
t
PU
0
0
0
0
ns
5
Power down time
t
PD
10
12
15
20
ns
5
Undefined/don't care
Falling input
Rising input
t
OH
t
AA
t
RC
t
OH
Data
OUT
Address
Data valid
Previous data valid
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