July 2005
ASM5I9350
rev 0.2
Alliance Semiconductor
2575, Augustine Drive
Santa Clara, CA
Tel: 408.855.4900
Fax: 408.855.4999
www.alsc.com
Notice: The information in this document is subject to change without notice.
3.3V 1:10 LVCMOS PLL Clock Generator
Features
Output frequency range: 25 MHz to 200 MHz
Input frequency range: 6.25 MHz to 31.25 MHz
2.5V or 3.3V operation
Split 2.5V/3.3V outputs
2.5% max Output duty cycle variation
Nine Clock outputs: Drive up to 18 clock lines
Two reference clock inputs: Xtal or LVCMOS
150pS max output-output skew
Phase-locked loop (PLL) bypass mode
`SpreadTrak'
Output
enable/disable
Pin-compatible with MPC9350 and CY29350.
Industrial temperature range: 40C to +85C
32-pin 1.0mm TQFP & LQFP Packages
Functional Description
The ASM5I9350 is a low-voltage high-performance
200MHz PLL-based clock driver designed for high speed
clock distribution applications.
The ASM5I9350 features Xtal and LVCMOS reference
clock inputs and provides nine outputs partitioned in four
banks of 1, 1, 2, and 5 outputs. Bank A divides the VCO
output by 2 or 4 while the other banks divide by 4 or 8 per
SEL(A:D) settings, see Table 2. These dividers allow
output to input ratios of 16:1, 8:1, 4:1, and 2:1. Each
LVCMOS compatible output can drive 50 series or
parallel terminated transmission lines. For series
terminated transmission lines, each output can drive one or
two traces giving the device an effective fanout of 1:18.
The PLL is ensured stable given that the VCO is configured
to run between 200MHz to 500MHz. This allows a wide
range of output frequencies from 25MHz to 200MHz. The
internal VCO is running at multiples of the input reference
clock set by the feedback divider, see Table 1.
When PLL_EN is LOW, PLL is bypassed and the reference
clock directly feeds the output dividers. This mode is fully
static and the minimum input clock frequency specification
does not apply.
July 2005
ASM5I9350
rev 0.2
3.3V 1:10 LVCMOS PLL Clock Generator
3 of 12
Notice: The information in this document is subject to change without notice.
Pin Discription
1
Pin #
Pin Name
I/O
Type
Description
8
XOUT
O
Analog
Oscillator Output
. Connect to a crystal.
9
XIN
I
Analog
Oscillator Input
. Connect to a crystal.
30
TCLK
I, PD
LVCMOS
LVCMOS/LVTTL reference clock input
28
QA
O
LVCMOS
Clock output bank A
26
QB
O
LVCMOS
Clock output bank B
22, 24
QC(1:0)
O
LVCMOS
Clock output bank C
12, 14, 16,
18, 20
QD(4:0)
O
LVCMOS
Clock output bank D
2
FB_SEL
I, PD
LVCMOS
Internal Feedback Select Input
. See
Table 1
.
10
OE#
I, PD
LVCMOS
Output enable/disable input
. See
Table 2
.
31
PLL_EN
I, PU
LVCMOS
PLL enable/disable input
. See
Table 2
.
32
REF_SEL
I, PD
LVCMOS
Reference select input
. See
Table 2
.
3, 4, 5, 6
SEL(A:D)
I, PD
LVCMOS
Frequency select input, Bank (A:D)
. See
Table 2
.
27
VDDQB
Supply
VDD
2.5V or 3.3V Power supply for bank B output clock
2,3
23
VDDQC
Supply
VDD
2.5V or 3.3V Power supply for bank C output clocks
2,3
15, 19
VDDQD
Supply
VDD
2.5V or 3.3V Power supply for bank D output clocks
2,3
1
AVDD
Supply
VDD
2.5V or 3.3V Power supply for PLL
2,3
11
VDD
Supply
VDD
2.5V or 3.3V Power supply for core, inputs, and bank A
output clock
2,3
7
AVSS
Supply
Ground
Analog ground
13, 17, 21,
25, 29
VSS
Supply
Ground
Common ground
Note: 1. PU = Internal pull-up, PD = Internal pull-down.
2. A 0.1F bypass capacitor should be placed as close as possible to each positive power pin (<0.2"). If these bypass capacitors are not close to the pins
their high frequency filtering characteristics will be cancelled by the lead inductance of the traces.
3. AVDD and VDD pins must be connected to a power supply level that is at least equal or higher than that of VDDQB, VDDQC, and VDDQD output
power supply pins.
Table 1: Frequency Table
FB_SEL
Feedback Divider
VCO
Input Frequency
Range (AVDD = 3.3V)
Input Frequency
Range (AVDD = 2.5V)
0
32
Input Clock * 32
6.25 MHz to 15.625 MHz
6.25 MHz to 11.875 MHz
1
16
Input Clock * 16
12.5 MHz to 31.25 MHz
12.5 MHz to 23.75 MHz
July 2005
ASM5I9350
rev 0.2
3.3V 1:10 LVCMOS PLL Clock Generator
4 of 12
Notice: The information in this document is subject to change without notice.
Table 2: Function Table
Control
Default
0
1
REF_SEL 0
Xtal
TCLK
PLL_EN 1
Bypass mode, PLL disabled. The
input clock connects to the output
dividers
PLL enabled. The VCO output connects to
the output dividers
OE# 0
Outputs
enabled
Outputs disabled (three-state)
FB_SEL
0
Feedback divider 32
Feedback divider 16
SELA
0
2 (Bank A)
4 (Bank A)
SELB
0
4 (Bank B)
8 (Bank B)
SELC 0
4 (Bank C
)
8 (Bank C)
SELD
0
4 (Bank D)
8 (Bank D)
Absolute Maximum Ratings
Parameter
Description
Condition
Min
Max
Unit
V
DD
DC Supply Voltage
0.3 5.5 V
V
DD
DC Operating Voltage
Functional 2.375
3.465
V
V
IN
DC Input Voltage
Relative to V
SS
0.3 V
DD
+ 0.3
V
V
OUT
DC Output Voltage
Relative to V
SS
0.3 V
DD
+ 0.3
V
V
TT
Output termination Voltage
V
DD
2 V
LU
Latch Up Immunity
Functional
200
mA
R
PS
Power Supply Ripple
Ripple Frequency < 100 kHz
150 mVp-p
T
S
Temperature, Storage
Non-functional 65
+150
C
T
A
Temperature, Operating Ambient Functional
40 +85 C
T
J
Temperature, Junction
Functional
+150 C
JC
Dissipation, Junction to Case
Functional
42 C/W
JA
Dissipation, Junction to Ambient
Functional
105 C/W
ESD
H
ESD Protection (Human Body Model)
2000
Volts
FIT
Failure in Time
Manufacturing test
10
ppm
July 2005
ASM5I9350
rev 0.2
3.3V 1:10 LVCMOS PLL Clock Generator
5 of 12
Notice: The information in this document is subject to change without notice.
DC Electrical Specifications
(V
CC
= 2.5V 5%, T
A
= -40C to +85C)
Parameter
Description
Condition
Min
Typ
Max
Unit
V
IL
Input Voltage, Low
LVCMOS
-
-
0.7
V
V
IH
Input Voltage, High
LVCMOS
1.7
-
V
DD
+0.3 V
V
OL
Output Voltage, Low
1
I
OL
= 15mA
-
-
0.6
V
V
OH
Output Voltage, High
1
I
OH
= 15mA
1.8
-
-
V
I
IL
Input Current, Low
2
V
IL
= V
SS
- - -100
A
I
IH
Input Current, High
2
V
IL
= V
DD
- - 100
A
I
DDA
PLL Supply Current
AVDD only
-
5
10
mA
I
DDQ
Quiescent Supply Current
All VDD pins except AVDD
-
-
7
mA
Outputs loaded @ 100 MHz
-
180
-
I
DD
Dynamic Supply Current
Outputs loaded @ 200 MHz
-
210
-
mA
C
IN
Input Pin Capacitance
- 4 - pF
Z
OUT
Output Impedance
14 18 22
Note: 1. Driving one 50 parallel terminated transmission line to a termination voltage of V
TT
. Alternatively, each output drives up to two 50 series terminated
transmission lines.
2. Inputs have pull-up or pull-down resistors that affect the input current.
DC Electrical Specifications
(V
CC
= 3.3V 5%, T
A
= -40C to +85C)
Parameter
Description
Condition
Min
Typ
Max
Unit
V
IL
Input Voltage, Low
LVCMOS
-
-
0.8
V
V
IH
Input Voltage, High
LVCMOS
2.0
-
V
DD
+0.3 V
I
OL
= 24 mA
-
-
0.55
V
OL
Output Voltage, Low
1
I
OL
= 12 mA
-
-
0.30
V
V
OH
Output Voltage, High
1
I
OH
= 24 mA
2.4
-
-
V
I
IL
Input Current, Low
2
V
IL
= V
SS
- -
100
A
I
IH
Input Current, High
2
V
IL
= V
DD
- - 100
A
I
DDA
PLL Supply Current
AVDD only
-
5
10
mA
I
DDQ
Quiescent Supply Current
All VDD pins except AVDD
-
-
7
mA
Outputs loaded @ 100 MHz
-
270
-
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