www.docs.chipfind.ru
July 2005
ASM5I9351
rev 0.2
Alliance Semiconductor
2575, Augustine Drive
Santa Clara, CA
Tel: 408.855.4900
Fax: 408.855.4999
www.alsc.com
Notice: The information in this document is subject to change without notice.
2.5V or 3.3V, 200 MHz, 9-Output Zero Delay Buffer
Features
Output frequency range: 25 MHz to 200 MHz
Input frequency range: 25 MHz to 200 MHz
2.5V or 3.3V operation
Split 2.5V/3.3V outputs
2.5% max Output duty cycle variation
Nine Clock outputs: Drive up to 18 clock lines
Two reference clock inputs: LVPECL or LVCMOS
150-ps max output-output skew
Phase-locked loop (PLL) bypass mode
`SpreadTrak'
Output
enable/disable
Pin-compatible with MPC9351 and CY29351.
Industrial temperature range: 40C to +85C
32-pin 1.0mm TQFP & LQFP Package.
Functional Description
The ASM5I9351 is a low voltage high performance
200MHz PLL-based zero delay buffer designed for high
speed clock distribution applications.
The ASM5I9351 features LVPECL and LVCMOS reference
clock inputs and provides 9 outputs partitioned in 4 banks
of 1, 1, 2, and 5 outputs. Bank A divides the VCO output by
2 or 4 while the other banks divide by 4 or 8 per SEL(A:D)
settings, see Table.2. These dividers allow output to input
ratios of 4:1, 2:1, 1:1, 1:2, and 1:4. Each LVCMOS
compatible output can drive 50 series or parallel
terminated transmission lines. For series terminated
transmission lines, each output can drive one or two traces
giving the device an effective fanout of 1:18.
The PLL is ensured stable given that the VCO is configured
to run between 200 MHz to 500 MHz. This allows a wide
range of output frequencies from 25 MHz to 200 MHz. For
normal operation, the external feedback input, FB_IN, is
connected to one of the outputs. The internal VCO is
running at multiples of the input reference clock set by the
feedback divider, see the Table 1.
When PLL_EN is LOW, PLL is bypassed and the reference
clock directly feeds the output dividers. This mode is fully
static and the minimum input clock frequency specification
does not apply.
July 2005
ASM5I9351
rev 0.2
2.5V or 3.3V, 200 MHz, 9-Output Zero Delay Buffer
2 of 13
Notice: The information in this document is subject to change without notice.
Block Diagram
Pin Configuration
1
2
3
4
5
6
7
8
32 31 30 29 28 27 26 25
9 10 11 12 13 14 15 16
24
23
22
21
20
19
18
17
FB_IN
SELA
SELB
SELC
SELD
AVSS
PECL_CLK
AVDD
REF_SEL
TCLK
VSS
QA
VDDQB
QB
VSS
PECL_CLK#
OE#
VDD
QD4
VSS
QD3
VDDQD
QD2
VDDQD
QD0
VSS
QC1
VDDQC
QC0
QD1
VSS
ASM5I9351
PLL_
EN
SELA
QD0
QD1
QD2
QD3
QD4
QC0
QC1
+4/
+8
+4/
+8
VCO
200-500MHz
Phase
Detector
LPF
PECL_CLK
FB_IN
SELB
SELD
OE#
+4/
+8
QB
+2/
+4
QA
PLL_EN
REF_SEL
TCLK
SELC
July 2005
ASM5I9351
rev 0.2
2.5V or 3.3V, 200 MHz, 9-Output Zero Delay Buffer
3 of 13
Notice: The information in this document is subject to change without notice.
Pin Configuration
1
Pin #
Pin Name
I/O
Type
Description
8
PECL_CLK
I, PU
Analog
LVPECL reference clock input
.
9
PECL_CLK#
I, PU/PD Analog
LVPECL reference clock input
. Weak pull-up to VDD/2.
30
TCLK
I, PD
LVCMOS
LVCMOS/LVTTL reference clock input
28
QA
O
LVCMOS
Clock output bank A
26
QB
O
LVCMOS
Clock output bank B
22, 24
QC(1:0)
O
LVCMOS
Clock output bank C
12, 14, 16, 18,
20
QD(4:0)
O
LVCMOS
Clock output bank D
2
FB_IN
I, PD
LVCMOS
Feedback clock input
. Connect to an output for normal
operation. This input should be at the same voltage rail as
input reference clock. See
Table 1
.
10
OE#
I, PD
LVCMOS
Output enable/disable input
. See
Table 2
.
31
PLL_EN
I, PU
LVCMOS
PLL enable/disable input
. See
Table 2
.
32
REF_SEL
I, PD
LVCMOS
Reference select input
. See
Table 2
.
3, 4, 5, 6
SEL(A:D)
I, PD
LVCMOS
Frequency select input, Bank (A:D)
. See
Table 2
.
27
VDDQB
Supply
VDD
2.5V or 3.3V Power supply for bank B output clock
2,3
23
VDDQC
Supply
VDD
2.5V or 3.3V Power supply for bank C output clocks
2,3
15, 19
VDDQD
Supply
VDD
2.5V or 3.3V Power supply for bank D output clocks
2,3
1
AVDD
Supply
VDD
2.5V or 3.3V Power supply for PLL
2,3
11
VDD
Supply
VDD
2.5V or 3.3V Power supply for core, inputs, and bank A
output clock
2,3
7
AVSS
Supply
Ground
Analog ground
13, 17, 21, 25,
29
VSS
Supply
Ground
Common ground
Note: 1
PU = Internal pull-up, PD = Internal pull-down.
2. A 0.1F bypass capacitor should be placed as close as possible to each positive power pin (<0.2"). If these bypass capacitors are not close to the pins
their high frequency filtering characteristics will be cancelled by the lead inductance of the traces.
3. AVDD and VDD pins must be connected to a power supply level that is at least equal or higher than that of VDDQB, VDDQC, and VDDQD output
power supply pins.
July 2005
ASM5I9351
rev 0.2
2.5V or 3.3V, 200 MHz, 9-Output Zero Delay Buffer
4 of 13
Notice: The information in this document is subject to change without notice.
Table 1: Frequency Table
Feedback Output
Divider
VCO
Input Frequency Range
(AVDD = 3.3V)
Input Frequency Range
(AVDD = 2.5V)
2
Input Clock * 2
100 MHz to 200 MHz
100 MHz to 190MHz
4
Input Clock * 4
50 MHz to 125 MHz
50 MHz to 95MHz
8
Input Clock * 8
25 MHz to 62.5 MHz
25 MHz to 47.5MHz
Table 2: Function Table
Control
Default
0
1
REF_SEL 0
PCLK
TCLK
PLL_EN 1
Bypass mode, PLL disabled. The
input clock connects to the output
dividers
PLL enabled. The VCO output connects to
the output dividers
OE# 0
Outputs
enabled
Outputs disabled (three-state), VCO running
at its minimum frequency
SELA
0
2 (Bank A)
4 (Bank A)
SELB
0
4 (Bank B)
8 (Bank B)
SELC 0
4 (Bank C
)
8 (Bank C)
SELD
0
4 (Bank D)
8 (Bank D)
Absolute Maximum Ratings
Parameter
Description
Condition
Min
Max
Unit
V
DD
DC Supply Voltage
0.3 5.5 V
V
DD
DC Operating Voltage
Functional 2.375
3.465
V
V
IN
DC Input Voltage
Relative to V
SS
0.3 V
DD
+ 0.3
V
V
OUT
DC Output Voltage
Relative to V
SS
0.3 V
DD
+ 0.3
V
V
TT
Output termination Voltage
V
DD
2 V
LU
Latch Up Immunity
Functional
200
mA
R
PS
Power Supply Ripple
Ripple Frequency < 100 kHz
150 mVp-p
T
S
Temperature, Storage
Non-functional 65
+150
C
T
A
Temperature, Operating Ambient Functional
40 +85 C
T
J
Temperature, Junction
Functional
+150 C
JC
Dissipation, Junction to Case
Functional
42
C/W
JA
Dissipation, Junction to Ambient
Functional
105
C/W
ESD
H
ESD Protection (Human Body Model)
2000
Volts
FIT
Failure in Time
Manufacturing test
10
ppm
Note: These are stress ratings only and functional operation is not implied. Exposure to absolute maximum ratings for extended periods may affect device
reliability.
July 2005
ASM5I9351
rev 0.2
2.5V or 3.3V, 200 MHz, 9-Output Zero Delay Buffer
5 of 13
Notice: The information in this document is subject to change without notice.
DC Electrical Specifications
(V
DD
= 2.5V 5%, T
A
= -40C to +85C)
Parameter
Description
Condition
Min
Typ
Max
Unit
V
IL
Input Voltage, Low
LVCMOS
-
-
0.7
V
V
IH
Input Voltage, High
LVCMOS
1.7
-
V
DD
+0.3 V
V
PP
Peak-Peak Input Voltage
LVPECL
250
-
1000
mV
V
CMR
Common Mode Range
1
LVPECL
1.0
- V
DD
0.6
V
V
OL
Output Voltage, Low
2
I
OL
= 15mA
-
-
0.6
V
V
OH
Output Voltage, High
2
I
OH
= 15mA
1.8
-
-
V
I
IL
Input Current, Low
3
V
IL
= V
SS
- - -100
A
I
IH
Input Current, High
3
V
IL
= V
DD
- - 100
A
I
DDA
PLL Supply Current
AVDD only
-
5
10
mA
I
DDQ
Quiescent Supply Current
All VDD pins except AVDD
-
-
7
mA
Outputs loaded @ 100 MHz
-
180
-
I
DD
Dynamic Supply Current
Outputs loaded @ 200 MHz
-
210
-
mA
C
IN
Input Pin Capacitance
- 4 - pF
Z
OUT
Output Impedance
14 18 22
Note: 1
V
CMR
(DC) is the crossing point of the differential input signal. Normal operation is obtained when the crossing point is within the V
CMR
range and the
input swing is within the V
PP
(DC) specification.
2.Driving one 50 parallel terminated transmission line to a termination voltage of V
TT
. Alternatively, each output drives up to two 50 series terminated
transmission lines.
3.Inputs have pull-up or pull-down resistors that affect the input current.
DC Electrical Specifications
(V
DD
= 3.3V 5%, T
A
= -40C to +85C)
Parameter
Description
Condition
Min
Typ
Max
Unit
V
IL
Input Voltage, Low
LVCMOS
-
-
0.8
V
V
IH
Input Voltage, High
LVCMOS
2.0
-
V
DD
+0.3 V
V
PP
Peak-Peak Input Voltage
LVPECL
250
-
1000
mV
V
CMR
Common Mode Range
1
LVPECL
1.0
- V
DD
0.6
V
I
OL
= 24 mA
-
-
0.55
V
OL
Output Voltage, Low
2
I
OL
= 12 mA
-
-
0.30
V
V
OH
Output Voltage, High
2
I
OH
= 24 mA
2.4
-
-
V
I
IL
Input Current, Low
3
V
IL
= V
SS
- -
100
A
I
IH
Input Current, High
3
V
IL
= V
DD
- - 100
A
I
DDA
PLL Supply Current
AVDD only
-
5
10
mA
I
DDQ
Quiescent Supply Current
All VDD pins except AVDD
-
-
7
mA
Outputs loaded @ 100 MHz
-
270
-
I
DD
Dynamic Supply Current
Outputs loaded @ 200 MHz
-
300
-
mA
C
IN
Input Pin Capacitance
- 4 - pF
Z
OUT
Output Impedance
12 15 18
Note: 1
V
CMR
(DC) is the crossing point of the differential input signal. Normal operation is obtained when the crossing point is within the V
CMR
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