June 2005
ASM5I9774A
rev 0.3
Alliance Semiconductor
2575, Augustine Drive
Santa Clara, CA Tel: 408.855.4900 Fax: 408.855.4999 www.alsc.com
Notice: The information in this document is subject to change without notice.
2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer
Features
Output frequency range: 8.3MHz to 125MHz
Input frequency range: 4.2MHz to 62.5MHz
2.5V or 3.3V operation
Split 2.5V/3.3V outputs
14 Clock outputs: Drive up to 28 clock lines
1 Feedback clock output
2 LVCMOS reference clock inputs
150 pS max output-output skew
PLL bypass mode
`SpreadTrak'
Output
enable/disable
Pin compatible with MPC9774 and CY29774AI.
Industrial temperature range: 40C to +85C
52Pin 1.0mm TQFP package
RoHS Compliance
Functional Description
The ASM5I9774A is a low-voltage high-performance
125MHz PLL-based zero delay buffer designed for high-
speed clock distribution applications.
The ASM5I9774A features two reference clock inputs and
provides 14 outputs partitioned in 3 banks of 5, 5, and 4
outputs. Bank A and Bank B divide the VCO output by 4 or
8 while Bank C divides by 8 or 12 per SEL(A:C) settings,
see Functional Table. These dividers allow output to input
ratios of 6:1, 4:1, 3:1, 2:1, 3:2, 4:3, 1:1, and 2:3. Each
LVCMOS compatible output can drive 50 series or
parallel terminated transmission lines. For series
terminated transmission lines, each output can drive one or
two traces giving the device an effective fanout of 1:28.
The PLL is ensured stable given that the VCO is configured
to run between 200 MHz to 500 MHz. This allows a wide
range of output frequencies from 8.3 MHz to 125 MHz. For
normal operation, the external feedback input, FB_IN, is
connected to the feedback output, FB_OUT. The internal
VCO is running at multiples of the input reference clock set
by the feedback divider, see Frequency Table.
When PLL_EN is LOW, PLL is bypassed and the reference
clock directly feeds the output dividers. This mode is fully
static and the minimum input clock frequency specification
does not apply.
Block Diagram
CLK
STOP
CLK
STOP
CLK
STOP
+2/+4
+2/+4
+4/+6
+4/+6/+8/+12
PLL
200-
500MHZ
VCO_SEL
QC3
QC2
QC1
QC0
QB3
QB2
QB1
QB0
QA3
QA2
QA1
QA0
QA4
QB4
FB_OUT
+2
+4
PLL_EN
TCLK_SEL
TCLK1
TCLK0
FB_IN
SELA
SELB
SELC
CLK_STP#
FB_SEL(1.0)
MR#/OE
June 2005
ASM5I9774A
rev 0.3
2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer
2 of 12
Notice: The information in this document is subject to change without notice.
Pin Configuration
VCO
_
SEL
VSS
QC0
V
DDQC
QC1
V
SS
QC2
V
DDQC
QC3
V
SS
NC
FB_SEL0
AVSS
QA
4
VDDQ
A
QA
3
VSS
FB_SEL1
QA
2
VDDQ
A
QA
1
VSS
QA
0
VDDQ
A
VSS
1
2
4
3
5
6
7
8
9
10
11
52 51 50 49 48 47 46 45 44 41
40
14 15 16 17 18 19 20 21 22 23 24
39
38
37
36
35
34
33
32
31
30
29
MR#/OE
CLK_STP#
SELC
PLL_EN
SELA
TCLK_SEL
TCLK0
TCLK1
NC
SELB
FB_IN
QB4
VDDQB
QB3
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