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Электронный компонент: P2005X-08TR

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October 2003
P2005A/S

rev 1.0
Alliance Semiconductor
2575, Augustine Drive
Santa Clara, CA
Tel: 408.855.4900
Fax: 408.855.4999
www.alsc.com
Notice: The information in this document is subject to change without notice.
Low Frequency EMI Reduction IC
Features
FCC approved method of EMI attenuation.
Provides up to 15dB of EMI suppression.
Generates a 1X or X low EMI spread spectrum
clock of the input frequency.
Input frequency range: 8MHz to 32MHz.
Internal loop filter minimizes external components
and board space.
Frequency deviation:
o
P2005A: 1% to 3%
o
P2005S: 0.6% to 1.8%
SSON# control pin for spread spectrum enable
and disable options.
Low cycle-to-cycle jitter.
3.3V or 5V operating voltage range.
16mA output drives.
TTL or CMOS compatible outputs.
Ultra-low power CMOS design.
Available in 8-pin SOIC and TSSOP.
Product Description
The P2005X is a versatile spread spectrum frequency
modulator designed specifically for input clock
frequencies from 8MHz to 32MHz.
Refer Output
Frequency Selection Table.
The P2005X can generate an
EMI reduced clock from crystal, ceramic resonator, or
system clock. The P2005X offers various percentage
deviations ranging form 0.6% to 3.0%.
Refer
Frequency Deviation Selections Table.
The P2005X
reduces electromagnetic interference (EMI) at the clock
source, allowing system wide reduction of EMI of down
stream clock and data dependent signals. The P2005X
allows significant system cost savings by reducing the
number of circuit board layers ferrite beads, shielding
and other passive components that are traditionally
required to pass EMI regulations.

The P2005X uses the most efficient and optimized
modulation profile approved by the FCC and is
implemented in a proprietary all digital method.

The P2005X modulates the output of a single PLL in
order to "spread" the bandwidth of a synthesized clock,
and more importantly, decreases the peak amplitudes of
its harmonics. This results in significantly lower system
EMI compared to the typical narrow band signal produced
by oscillators and most frequency generators. Lowering
EMI by increasing a signal's bandwidth is called `spread
spectrum clock generation'.

Applications
The P2005X is targeted towards EMI management for
high-speed digital applications such as PC peripheral
devices, consumer electronics and embedded controller
systems.

Block Diagram
VSS
XIN
Frequency
Divider
Feedback
Divider
Modulation
Phase
Detector
Loop
Filter
VCO
Output
Divider
MODOUT
PLL
VDD
SSON#
DIV2
SR0
Crystal
Oscillator
XOUT
October 2003
P2005X

rev 1.0
General purpose EMI Reduction IC
2 of 10
Notice: The information in this document is subject to change without notice.
XOUT
1
2
3
4
5
6
7
8
P2005X
XIN /CLK
DIV2
VSS
SR0
SSON#
ModOUT
VDD

Pin Configuration









Pin Description
Pin#
Pin
Name
Type
Description
1
XIN/CLK
I
Connect to crystal or clock.
2 XOUT O
Crystal
output.
3 DIV2 I
Digital logic input used to select normal output mode or divide-by-two output mode.
When this pin is HIGH, the frequency of the output clock is the same as the input
clock frequency. When it is tied low, the output frequency is half the input clock
frequency. This pin has an internal pull-up resistor.
4
VSS
P
Ground to entire chip. Connect to system ground.
5 SR0 I
Digital logic input used to select Spreading Range
Refer Modulation Output and
Spreading Range Selection Table
. This pin has an internal pull-up resistor.
6 SSON# I
Digital logic input used to enable Spread Spectrum function (Active LOW). Spread
Spectrum function enabled when LOW, disabled when HIGH. This pin has an internal
pull-low resistor.
7
ModOUT
O
Spread spectrum clock output.
8
VDD
P
Power supply for the entire chip (+3.3V or 5.0V)

Output Frequency Selections
Input Frequency
8 MHz
12 MHz 16 MHz 20 MHz 24 MHz 28 MHz 32 MHz
0 (1/2 X)
4 MHz
6 MHz
8 MHz
10 MHz 12 MHz 14 MHz 16 MHz
DIV2
1 (1X)
8 MHz
12 MHz 16 MHz 20 MHz 24 MHz 28 MHz 32 MHz
Output
Frequency

Frequency Deviation Selections as a Function of Input Frequency
Input Frequency Range
P/N
SR0
8 MHz
12 MHz
16 MHz
20 MHz
24 MHz
28 MHz
32 MHz
Modulation
Rate (KHz)
0
3.0%
2.5%
2.0%
1.8%
1.5%
1.5%
1.3%
P2005A
1
2.5%
2.0%
1.8%
1.5%
1.3%
1.3%
1.0%
0
1.8%
1.5%
1.2%
1.1%
0.9%
0.9%
0.8%
P2005S
1
1.5%
1.2%
1.1%
0.9%
0.8%
0.8%
0.6%
(X
IN
/20) * 62.5
October 2003
P2005X

rev 1.0
General purpose EMI Reduction IC
3 of 10
Notice: The information in this document is subject to change without notice.


Spread Spectrum
The
Output Frequency Selection Table and the Frequency Deviations Selections Table
illustrate the two
possible spread spectrum options. The optimal setting should minimize system EMI to the fullest without
affecting system performance. The spreading is described as a percentage deviation of the center frequency
(Note: The center frequency is the frequency of the external reference input on CLKIN, Pin1).

Example:
The P2005X is designed for communications, digital video and imaging applications. It is not only optimized for
operation in the 8MHz 32MHz range, but its output frequency can be extended down to one half of the input
clock frequency using the divide-by-two feature. This feature extends low frequency as low as to 4MHz. Setting
Pin 3 low (DIV2 = 0; Divide-by-two mode) sets the output frequency (ModOUT) to half the frequency of the input
clock (CLKIN). This is a simple way to generate a spread spectrum modulated low frequency clock when only a
higher frequency signal is available. If you want the output frequency to be the same as the input, you can either
set DIV2=1 or leave it unconnected.

Selecting the P2005X's spread options is a matter of either setting SR0=1 or SR0=0. Setting SR0=0 set as a
lower modulation spread, while setting it to 1 introduces a wider spectral spread in the output clock.
Refer
Modulation output and Spreading Selections Tables.
The example given in the figure below shows the device
set to the divide-by-two mode (DIV2=0) with a lower spectrum range (SR0=0). The versatility provided by
allowing both clock division and spread spectrum on one chip is already proving to be a popular solution among
leading system manufacturers.
P2005X Application Schematic
1
2
3
4
CLKIN
XOUT
DIV2
VSS
MODOUT
5
6
7
8
SR0
SSON#
VDD
8.832MHz Crystal
Modulated 4.416MHz is
connected to CLK input
pin of the system
+3.3V
0.1F
P2005X
October 2003
P2005X

rev 1.0
General purpose EMI Reduction IC
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Notice: The information in this document is subject to change without notice.


EMC Software Simulation
By using Alliance's proprietary EMC simulation software EMI-Lator, radiated system level EMI analysis can
be made easier, allowing quantitative measure on the benefits of Alliance's EMI reduction products. The
simulation engine of this EMC software has already been characterized to correlate with the electrical
characteristics of Alliance EMI reduction ICs. The figure below is an illustration of this simulation result.

Please visit our website at
www.alsc.com
for information on how to obtain a free copy and demonstration of
EMI-Lator .
Simulation results From EMI-Lator









October 2003
P2005X

rev 1.0
General purpose EMI Reduction IC
5 of 10
Notice: The information in this document is subject to change without notice.


Absolute Maximum Ratings
Symbol
Parameter
Rating
Unit
V
DD
, V
IN
Voltage on any pin with respect to GND
-0.5 to + 7.0
V
T
STG
Storage
temperature
-65 to +125
C
T
A
Operating
temperature
0 to 70
C
Note: These are stress ratings only and functional operation is not implied. Exposure to absolute maximum
ratings for extended periods may affect device reliability.




DC Electrical Characteristics
Symbol
Parameter
Min
Typ
Max
Unit
V
IL
Input low voltage
GND 0.3
-
0.8
V
V
IH
Input high voltage
2.0
-
V
DD
+ 0.3
V
I
IL
Input low current (pull-up resistors on inputs SR0, SR1,
CP0 and CP1)
- -
-35
A
I
IH
Input high current (pull-down resistor on input SSON#)
-
-
35
A
I
XOL
XOUT Output Low Current (@ 0.4V, V
DD
= 3.3V)
-
3
-
mA
I
XOH
XOUT Output High Current (@ 2.5V, V
DD
= 3.3V)
3
V
OL
Output low voltage (V
DD
= 3.3V, I
OL
= 20mA)
-
-
0.4
V
V
OH
Output high voltage (V
DD
= 3.3V, I
OH
= 20mA)
2.5
-
-
V
I
CC
Dynamic supply current normal mode (3.3V, and 15pF
loading)
6.0 7.0 8.3
mA
I
DD
Static supply current standby mode
-
0.6
-
mA
V
DD
Operating
voltage
3.1 3.3 5.5 V
t
ON
Power up time (first locked clock cycle after power up)
-
0.18
-
mS
Z
OUT
Clock output impedance
-
50
-