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Preliminary
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Preliminary
Contents
Chapter Revision Dates ........................................................................... xi
About this Handbook ............................................................................. xiii
How to Find Information ..................................................................................................................... xiii
How to Contact Altera .......................................................................................................................... xiii
Typographic Conventions .................................................................................................................... xiv
Section I. Cyclone FPGA Family Data Sheet
Revision History ....................................................................................................................... Section I1
Chapter 1. Introduction
Introduction ............................................................................................................................................ 11
Features ................................................................................................................................................... 12
Chapter 2. Cyclone Architecture
Functional Description .......................................................................................................................... 21
Logic Array Blocks ................................................................................................................................ 23
LAB Interconnects ............................................................................................................................ 23
LAB Control Signals ......................................................................................................................... 24
Logic Elements ....................................................................................................................................... 25
LUT Chain & Register Chain .......................................................................................................... 27
addnsub Signal ................................................................................................................................. 27
LE Operating Modes ........................................................................................................................ 27
MultiTrack Interconnect ..................................................................................................................... 212
Embedded Memory ............................................................................................................................. 218
Memory Modes ............................................................................................................................... 218
Parity Bit Support ........................................................................................................................... 220
Shift Register Support .................................................................................................................... 220
Memory Configuration Sizes ........................................................................................................ 221
Byte Enables .................................................................................................................................... 223
Control Signals & M4K Interface ................................................................................................. 223
Independent Clock Mode .............................................................................................................. 225
Input/Output Clock Mode ........................................................................................................... 225
Read/Write Clock Mode ............................................................................................................... 227
Single-Port Mode ............................................................................................................................ 228
Global Clock Network & Phase-Locked Loops ............................................................................... 229
Global Clock Network ................................................................................................................... 229
Dual-Purpose Clock Pins .............................................................................................................. 230
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Cyclone Device Handbook, Volume 1
Combined Resources ..................................................................................................................... 231
PLLs .................................................................................................................................................. 232
Clock Multiplication & Division .................................................................................................. 235
External Clock Inputs .................................................................................................................... 236
External Clock Outputs ................................................................................................................. 236
Clock Feedback ............................................................................................................................... 237
Phase Shifting ................................................................................................................................. 237
Lock Detect Signal .......................................................................................................................... 237
Programmable Duty Cycle ........................................................................................................... 238
Control Signals ................................................................................................................................ 238
I/O Structure ........................................................................................................................................ 239
External RAM Interfacing ............................................................................................................. 246
DDR SDRAM & FCRAM .............................................................................................................. 246
Programmable Drive Strength ..................................................................................................... 249
Open-Drain Output ........................................................................................................................ 250
Slew-Rate Control .......................................................................................................................... 250
Bus Hold .......................................................................................................................................... 251
Programmable Pull-Up Resistor .................................................................................................. 251
Advanced I/O Standard Support ................................................................................................ 252
LVDS I/O Pins ................................................................................................................................ 254
MultiVolt I/O Interface ................................................................................................................. 254
Power Sequencing & Hot Socketing ................................................................................................. 255
Chapter 3. Configuration & Testing
IEEE Std. 1149.1 (JTAG) Boundary Scan Support ............................................................................. 31
SignalTap II Embedded Logic Analyzer ............................................................................................ 35
Configuration ......................................................................................................................................... 35
Operating Modes .............................................................................................................................. 36
Configuration Schemes ................................................................................................................... 36
Chapter 4. DC & Switching Characteristics
Operating Conditions ........................................................................................................................... 41
Power Consumption ............................................................................................................................. 48
Timing Model ......................................................................................................................................... 49
Preliminary & Final Timing ............................................................................................................ 49
Internal Timing Parameters .......................................................................................................... 410
External Timing Parameters ......................................................................................................... 414
External I/O Delay Parameters .................................................................................................... 421
Maximum Input & Output Clock Rates ...................................................................................... 427
Chapter 5. Reference & Ordering Information
Software .................................................................................................................................................. 51
Device Pin-Outs ..................................................................................................................................... 51
Ordering Information ........................................................................................................................... 51
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Section II. Clock Management
Revision History ..................................................................................................................... Section II1
Chapter 6. Using PLLs in Cyclone Devices
Introduction ............................................................................................................................................ 61
Hardware Overview ........................................................................................................................ 61
Software Overview .......................................................................................................................... 64
Pins & Clock Network Connections .............................................................................................. 66
Hardware Features ................................................................................................................................ 68
Clock Multiplication & Division .................................................................................................... 68
Phase Shifting ................................................................................................................................... 69
Programmable Duty Cycle ........................................................................................................... 610
External Clock Output ................................................................................................................... 611
Control Signals ................................................................................................................................ 612
Clock Feedback Modes ....................................................................................................................... 613
Normal Mode .................................................................................................................................. 613
Zero Delay Buffer Mode ................................................................................................................ 614
No Compensation .......................................................................................................................... 615
Pins ......................................................................................................................................................... 616
Board Layout ........................................................................................................................................ 617
VCCA & GNDA ............................................................................................................................. 617
Jitter Considerations ...................................................................................................................... 619
Specifications ........................................................................................................................................ 620
Software Support ................................................................................................................................. 621
Quartus II altpll Megafunction ..................................................................................................... 621
altpll Input Ports ............................................................................................................................. 622
altpll Output Ports ......................................................................................................................... 623
MegaWizard Customization ......................................................................................................... 623
MegaWizard Page Description ..................................................................................................... 625
Compilation Report ....................................................................................................................... 631
Timing Analysis .............................................................................................................................. 633
Simulation ....................................................................................................................................... 637
Global Clock Network ........................................................................................................................ 638
Dedicated Clock Input Pins .......................................................................................................... 640
Dual-Purpose Clock I/O Pins ...................................................................................................... 640
Combined Sources .......................................................................................................................... 641
Conclusion ............................................................................................................................................ 643
Section III. Memory
Revision History .................................................................................................................... Section III1
Chapter 7. On-Chip Memory Implementations Using Cyclone Memory Blocks
Introduction ............................................................................................................................................ 71
M4K Memory Features ......................................................................................................................... 71
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