Copyright 2005 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device des-
ignations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and
service marks of Altera Corporation in the U.S. and other countries. All other product or service names are the property of their respective holders. Al-
tera products are protected under numerous U.S. and foreign patents and pending applications, maskwork rights, and copyrights. Altera warrants
performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make
changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the ap-
plication or use of any information, product, or service described herein except as expressly agreed to in writing by Altera
Corporation. Altera customers are advised to obtain the latest version of device specifications before relying on any published in-
formation and before placing orders for products or services
.
ii
Altera
Corporation
Altera Corporation
iii
Contents
Chapter Revision Dates .......................................................................... vii
About This Handbook .............................................................................. ix
How to Find Information ........................................................................................................................ ix
How to Contact Altera ............................................................................................................................. ix
Typographic Conventions ........................................................................................................................ x
Section I. Stratix Device Family Data Sheet
Revision History ............................................................................................................................ Part I1
Chapter 1. Introduction
Introduction ............................................................................................................................................ 11
Features ................................................................................................................................................... 12
Chapter 2. Stratix Architecture
Functional Description .......................................................................................................................... 21
Logic Array Blocks ................................................................................................................................ 23
LAB Interconnects ............................................................................................................................ 24
LAB Control Signals ......................................................................................................................... 25
Logic Elements ....................................................................................................................................... 26
LUT Chain & Register Chain .......................................................................................................... 28
addnsub Signal ................................................................................................................................. 28
LE Operating Modes ........................................................................................................................ 28
Clear & Preset Logic Control ........................................................................................................ 213
MultiTrack Interconnect ..................................................................................................................... 214
TriMatrix Memory ............................................................................................................................... 221
Memory Modes ............................................................................................................................... 222
Clear Signals .................................................................................................................................... 224
Parity Bit Support ........................................................................................................................... 224
Shift Register Support .................................................................................................................... 225
Memory Block Size ......................................................................................................................... 226
Independent Clock Mode .............................................................................................................. 244
Input/Output Clock Mode ........................................................................................................... 246
Read/Write Clock Mode ............................................................................................................... 249
Single-Port Mode ............................................................................................................................ 251
Multiplier Block .............................................................................................................................. 257
Adder/Output Blocks ................................................................................................................... 261
Modes of Operation ....................................................................................................................... 264
iv
Altera
Corporation
Contents
Stratix Device Handbook, Volume 1
DSP Block Interface ........................................................................................................................ 270
PLLs & Clock Networks ..................................................................................................................... 273
Global & Hierarchical Clocking ................................................................................................... 273
Enhanced & Fast PLLs ................................................................................................................... 281
Enhanced PLLs ............................................................................................................................... 287
Fast PLLs ........................................................................................................................................ 2100
I/O Structure ...................................................................................................................................... 2104
Double-Data Rate I/O Pins ......................................................................................................... 2111
External RAM Interfacing ........................................................................................................... 2115
Programmable Drive Strength ................................................................................................... 2119
Open-Drain Output ...................................................................................................................... 2120
Slew-Rate Control ........................................................................................................................ 2120
Bus Hold ........................................................................................................................................ 2121
Programmable Pull-Up Resistor ................................................................................................ 2122
Advanced I/O Standard Support .............................................................................................. 2122
Differential On-Chip Termination ............................................................................................. 2127
MultiVolt I/O Interface ............................................................................................................... 2129
High-Speed Differential I/O Support ............................................................................................ 2130
Dedicated Circuitry ...................................................................................................................... 2137
Byte Alignment ............................................................................................................................. 2140
Power Sequencing & Hot Socketing ............................................................................................... 2140
Chapter 3. Configuration & Testing
IEEE Std. 1149.1 (JTAG) Boundary-Scan Support ............................................................................ 31
SignalTap II Embedded Logic Analyzer ............................................................................................ 35
Configuration ......................................................................................................................................... 35
Operating Modes .............................................................................................................................. 35
Configuring Stratix FPGAs with JRunner .................................................................................... 37
Configuration Schemes ................................................................................................................... 37
Partial Reconfiguration .................................................................................................................... 37
Remote Update Configuration Modes .......................................................................................... 38
Stratix Automated Single Event Upset (SEU) Detection ................................................................ 312
Custom-Built Circuitry .................................................................................................................. 313
Software Interface ........................................................................................................................... 313
Temperature Sensing Diode ............................................................................................................... 313
Chapter 4. DC & Switching Characteristics
Operating Conditions ........................................................................................................................... 41
Power Consumption ........................................................................................................................... 417
Timing Model ....................................................................................................................................... 419
Preliminary & Final Timing .......................................................................................................... 419
Performance .................................................................................................................................... 420
Internal Timing Parameters .......................................................................................................... 422
External Timing Parameters ......................................................................................................... 433
Stratix External I/O Timing .......................................................................................................... 436
I/O Timing Measurement Methodology .................................................................................... 460
External I/O Delay Parameters .................................................................................................... 466
Altera Corporation
v
Contents
Contents
Maximum Input & Output Clock Rates ...................................................................................... 476
High-Speed I/O Specification ........................................................................................................... 487
PLL Specifications ................................................................................................................................ 494
DLL Jitter ............................................................................................................................................. 4102
Chapter 5. Reference & Ordering Information
Software .................................................................................................................................................. 51
Device Pin-Outs ..................................................................................................................................... 51
Ordering Information ........................................................................................................................... 51
Index
PDF 
ZIP