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.
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Preliminary
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Preliminary
Contents
Chapter Revision Dates .......................................................................... vii
About this Handbook ............................................................................... ix
How to Contact Altera ............................................................................................................................. ix
Typographic Conventions ....................................................................................................................... ix
Section I. Stratix II Device Family Data Sheet
Revision History ....................................................................................................................... Section I1
Chapter 1. Introduction
Introduction ............................................................................................................................................ 11
Features ................................................................................................................................................... 11
Chapter 2. Stratix II Architecture
Functional Description .......................................................................................................................... 21
Logic Array Blocks ................................................................................................................................ 23
LAB Interconnects ............................................................................................................................ 24
LAB Control Signals ......................................................................................................................... 25
Adaptive Logic Modules ...................................................................................................................... 26
ALM Operating Modes ................................................................................................................... 29
Register Chain ................................................................................................................................. 220
Clear & Preset Logic Control ........................................................................................................ 222
MultiTrack Interconnect ..................................................................................................................... 222
TriMatrix Memory ............................................................................................................................... 228
Memory Block Size ......................................................................................................................... 228
Digital Signal Processing Block ......................................................................................................... 240
Modes of Operation ....................................................................................................................... 244
DSP Block Interface ........................................................................................................................ 244
PLLs & Clock Networks ..................................................................................................................... 248
Global & Hierarchical Clocking ................................................................................................... 248
Enhanced & Fast PLLs ................................................................................................................... 256
Enhanced PLLs ............................................................................................................................... 268
Fast PLLs .......................................................................................................................................... 269
I/O Structure ........................................................................................................................................ 270
Double Data Rate I/O Pins ........................................................................................................... 278
External RAM Interfacing ............................................................................................................. 282
Programmable Drive Strength ..................................................................................................... 284
Open-Drain Output ........................................................................................................................ 285
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Stratix II Device Handbook, Volume 1
Contents
Bus Hold .......................................................................................................................................... 285
Programmable Pull-Up Resistor .................................................................................................. 286
Advanced I/O Standard Support ................................................................................................ 286
On-Chip Termination .................................................................................................................... 290
For more information on tolerance specifications for on-chip termination with calibration, refer
to the DC & Switching Characteristics chapter in Volume 1 of the Stratix II Device Handbook. ......
293
MultiVolt I/O Interface ................................................................................................................. 293
High-Speed Differential I/O with DPA Support ............................................................................ 295
Dedicated Circuitry with DPA Support ...................................................................................... 299
Fast PLL & Channel Layout ........................................................................................................ 2101
Chapter 3. Configuration & Testing
IEEE Std. 1149.1 JTAG Boundary-Scan Support ............................................................................... 31
SignalTap II Embedded Logic Analyzer ............................................................................................ 34
Configuration ......................................................................................................................................... 34
Operating Modes .............................................................................................................................. 34
Configuration Schemes ................................................................................................................... 36
Configuring Stratix II FPGAs with JRunner ................................................................................. 39
Programming Serial Configuration Devices with SRunner ....................................................... 39
Configuring Stratix II FPGAs with the MicroBlaster Driver ................................................... 310
PLL Reconfiguration ...................................................................................................................... 310
Temperature Sensing Diode ............................................................................................................... 310
Automated Single Event Upset (SEU) Detection ............................................................................ 312
Custom-Built Circuitry .................................................................................................................. 313
Software Interface ........................................................................................................................... 313
Chapter 4. Hot Socketing, ESD & Power-On Reset
Stratix II Hot-Socketing Specifications ............................................................................................... 41
Devices Can Be Driven before Power-Up ..................................................................................... 42
I/O Pins Remain Tri-Stated during Power-Up ............................................................................ 42
Signal Pins Do Not Drive the V
CCIO
, V
CCINT
or V
CCPD
Power Supplies .................................... 42
Hot Socketing Feature Implementation in Stratix II Devices .......................................................... 43
ESD Protection ....................................................................................................................................... 45
Power-On Reset Circuitry .................................................................................................................... 47
Chapter 5. DC & Switching Characteristics
Operating Conditions ........................................................................................................................... 51
Absolute Maximum Ratings ........................................................................................................... 51
Recommended Operating Conditions .......................................................................................... 52
DC Electrical Characteristics .......................................................................................................... 53
I/O Standard Specifications ........................................................................................................... 54
Bus Hold Specifications ................................................................................................................. 516
On-Chip Termination Specifications ........................................................................................... 517
Pin Capacitance .............................................................................................................................. 518
Power Consumption ........................................................................................................................... 519
Timing Model ....................................................................................................................................... 519
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Stratix II Device Handbook, Volume 1
Contents
Preliminary & Final Timing .......................................................................................................... 519
I/O Timing Measurement Methodology .................................................................................... 520
Performance .................................................................................................................................... 526
Internal Timing Parameters .......................................................................................................... 531
Stratix II Clock Timing Parameters .............................................................................................. 536
IOE Programmable Delay ............................................................................................................. 543
Default Capacitive Loading of Different I/O Standards .......................................................... 544
I/O Delays ....................................................................................................................................... 545
Maximum Input & Output Clock Rates ...................................................................................... 555
High-Speed I/O Specifications .......................................................................................................... 561
PLL Timing Specifications .................................................................................................................. 566
JTAG Timing Specifications ............................................................................................................... 568
Chapter 6. Reference & Ordering Information
Software .................................................................................................................................................. 61
Device Pin-Outs ..................................................................................................................................... 61
Ordering Information ........................................................................................................................... 61
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