Document Outline
- MAX 7000 Programmable Logic Device Family Data Sheet
Altera Corporation
1
MAX 7000
Programmable Logic
Device Family
December 2002, ver. 6.5
Data Sheet
DS-MAX7000-6.5
Features...
High-performance, EEPROM-based programmable logic devices
(PLDs) based on second-generation MAX
architecture
5.0-V in-system programmability (ISP) through the built-in
IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface available in
MAX 7000S devices
ISP circuitry compatible with IEEE Std. 1532
Includes 5.0-V MAX 7000 devices and 5.0-V ISP-based MAX 7000S
devices
Built-in JTAG boundary-scan test (BST) circuitry in MAX
7000S
devices with 128 or more macrocells
Complete EPLD family with logic densities ranging from 600 to
5,000 usable gates (see
Tables 1
and
2
)
5-ns pin-to-pin logic delays with up to 175.4-MHz counter
frequencies (including interconnect)
PCI-compliant devices available
f
For information on in-system programmable 3.3-V MAX 7000A or 2.5-V
MAX 7000B devices, see the
MAX 7000A Programmable Logic Device Family
Data Sheet
or the
MAX 7000B Programmable Logic Device Family Data
Sheet
.
Table 1. MAX 7000 Device Features
Feature
EPM7032
EPM7064
EPM7096
EPM7128E
EPM7160E
EPM7192E
EPM7256E
Usable
gates
600
1,250
1,800
2,500
3,200
3,750
5,000
Macrocells
32
64
96
128
160
192
256
Logic array
blocks
2
4
6
8
10
12
16
Maximum
user I/O pins
36
68
76
100
104
124
164
t
PD
(ns)
6
6
7.5
7.5
10
12
12
t
SU
(ns)
5
5
6
6
7
7
7
t
FSU
(ns)
2.5
2.5
3
3
3
3
3
t
CO1
(ns)
4
4
4.5
4.5
5
6
6
f
CNT
(MHz)
151.5
151.5
125.0
125.0
100.0
90.9
90.9
2
Altera Corporation
MAX 7000 Programmable Logic Device Family Data Sheet
...and More
Features
Open-drain output option in MAX 7000S devices
Programmable macrocell flipflops with individual clear, preset,
clock, and clock enable controls
Programmable power-saving mode for a reduction of over 50% in
each macrocell
Configurable expander product-term distribution, allowing up to
32 product terms per macrocell
44 to 208 pins available in plastic J-lead chip carrier (PLCC), ceramic
pin-grid array (PGA), plastic quad flat pack (PQFP), power quad flat
pack (RQFP), and 1.0-mm thin quad flat pack (TQFP) packages
Programmable security bit for protection of proprietary designs
3.3-V or 5.0-V operation
MultiVolt
TM
I/O interface operation, allowing devices to
interface with 3.3-V or 5.0-V devices (MultiVolt I/O operation is
not available in 44-pin packages)
Pin compatible with low-voltage MAX 7000A and MAX 7000B
devices
Enhanced features available in MAX 7000E and MAX 7000S devices
Six pin- or logic-driven output enable signals
Two global clock signals with optional inversion
Enhanced interconnect resources for improved routability
Fast input setup times provided by a dedicated path from I/O
pin to macrocell registers
Programmable output slew-rate control
Software design support and automatic place-and-route provided by
Altera's development system for Windows-based PCs and Sun
SPARCstation, and HP 9000 Series 700/800 workstations
Table 2. MAX 7000S Device Features
Feature
EPM7032S
EPM7064S
EPM7128S
EPM7160S
EPM7192S
EPM7256S
Usable gates
600
1,250
2,500
3,200
3,750
5,000
Macrocells
32
64
128
160
192
256
Logic array
blocks
2
4
8
10
12
16
Maximum
user I/O pins
36
68
100
104
124
164
t
PD
(ns)
5
5
6
6
7.5
7.5
t
SU
(ns)
2.9
2.9
3.4
3.4
4.1
3.9
t
FSU
(ns)
2.5
2.5
2.5
2.5
3
3
t
CO1
(ns)
3.2
3.2
4
3.9
4.7
4.7
f
CNT
(MHz)
175.4
175.4
147.1
149.3
125.0
128.2
Altera Corporation
3
MAX 7000 Programmable Logic Device Family Data Sheet
Additional design entry and simulation support provided by EDIF
2 0 0 and 3 0 0 netlist files, library of parameterized modules (LPM),
Verilog HDL, VHDL, and other interfaces to popular EDA tools from
manufacturers such as Cadence, Exemplar Logic, Mentor Graphics,
OrCAD, Synopsys, and VeriBest
Programming support
Altera's Master Programming Unit (MPU) and programming
hardware from third-party manufacturers program all
MAX 7000 devices
The BitBlaster
TM
serial download cable, ByteBlasterMV
TM
parallel port download cable, and MasterBlaster
TM
serial/universal serial bus (USB) download cable program MAX
7000S devices
General
Description
The MAX 7000 family of high-density, high-performance PLDs is based
on Altera's second-generation MAX architecture. Fabricated with
advanced CMOS technology, the EEPROM-based MAX 7000 family
provides 600 to 5,000 usable gates, ISP, pin-to-pin delays as fast as 5 ns,
and counter speeds of up to 175.4 MHz. MAX 7000S devices in the -5, -6,
-7, and -10 speed grades as well as MAX 7000 and MAX 7000E devices in
-5, -6, -7, -10P, and -12P speed grades comply with the PCI Special Interest
Group (PCI SIG) PCI Local Bus Specification, Revision 2.2. See
Table 3
for available speed grades.
Table 3. MAX 7000 Speed Grades
Device
Speed Grade
-5
-6
-7
-10P
-10
-12P
-12
-15
-15T
-20
EPM7032
v
v
v
v
v
v
EPM7032S
v
v
v
v
EPM7064
v
v
v
v
v
EPM7064S
v
v
v
v
EPM7096
v
v
v
v
EPM7128E
v
v
v
v
v
v
EPM7128S
v
v
v
v
EPM7160E
v
v
v
v
v
EPM7160S
v
v
v
v
EPM7192E
v
v
v
v
EPM7192S
v
v
v
EPM7256E
v
v
v
v
EPM7256S
v
v
v
4
Altera Corporation
MAX 7000 Programmable Logic Device Family Data Sheet
The MAX 7000E devices--including the EPM7128E, EPM7160E,
EPM7192E, and EPM7256E devices--have several enhanced features:
additional global clocking, additional output enable controls, enhanced
interconnect resources, fast input registers, and a programmable slew
rate.
In-system programmable MAX 7000 devices--called MAX 7000S
devices--include the EPM7032S, EPM7064S, EPM7128S, EPM7160S,
EPM7192S, and EPM7256S devices. MAX 7000S devices have the
enhanced features of MAX 7000E devices as well as JTAG BST circuitry in
devices with 128 or more macrocells, ISP, and an open-drain output
option. See
Table 4
.
Notes:
(1)
Available only in EPM7128S, EPM7160S, EPM7192S, and EPM7256S devices only.
(2)
The MultiVolt I/O interface is not available in 44-pin packages.
Table 4. MAX 7000 Device Features
Feature
EPM7032
EPM7064
EPM7096
All
MAX 7000E
Devices
All
MAX 7000S
Devices
ISP via JTAG interface
v
JTAG BST circuitry
v
(1)
Open-drain output option
v
Fast input registers
v
v
Six global output enables
v
v
Two global clocks
v
v
Slew-rate control
v
v
MultiVolt interface
(2)
v
v
v
Programmable register
v
v
v
Parallel expanders
v
v
v
Shared expanders
v
v
v
Power-saving mode
v
v
v
Security bit
v
v
v
PCI-compliant devices available
v
v
v
Altera Corporation
5
MAX 7000 Programmable Logic Device Family Data Sheet
The MAX 7000 architecture supports 100% TTL emulation and
high-density integration of SSI, MSI, and LSI logic functions. The
MAX 7000 architecture easily integrates multiple devices ranging from
PALs, GALs, and 22V10s to MACH and pLSI devices. MAX 7000 devices
are available in a wide range of packages, including PLCC, PGA, PQFP,
RQFP, and TQFP packages. See
Table 5
.
Notes:
(1)
When the JTAG interface in MAX 7000S devices is used for either boundary-scan testing or for ISP, four I/O pins
become JTAG pins.
(2)
Perform a complete thermal analysis before committing a design to this device package. For more information, see
the
Operating Requirements for Altera Devices Data Sheet
.
MAX 7000 devices use CMOS EEPROM cells to implement logic
functions. The user-configurable MAX 7000 architecture accommodates a
variety of independent combinatorial and sequential logic functions. The
devices can be reprogrammed for quick and efficient iterations during
design development and debug cycles, and can be programmed and
erased up to 100 times.
Table 5. MAX 7000 Maximum User I/O Pins
Note (1)
Device
44-
Pin
PLCC
44-
Pin
PQFP
44-
Pin
TQFP
68-
Pin
PLCC
84-
Pin
PLCC
100-
Pin
PQFP
100-
Pin
TQFP
160-
Pin
PQFP
160-
Pin
PGA
192-
Pin
PGA
208-
Pin
PQFP
208-
Pin
RQFP
EPM7032
36
36
36
EPM7032S
36
36
EPM7064
36
36
52
68
68
EPM7064S
36
36
68
68
EPM7096
52
64
76
EPM7128E
68
84
100
EPM7128S
68
84
84
(2)
100
EPM7160E
64
84
104
EPM7160S
64
84
(2)
104
EPM7192E
124
124
EPM7192S
124
EPM7256E
132
(2)
164
164
EPM7256S
164
(2)
164
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