Document Outline
- MAX 7000A Programmable Logic Device Data Sheet
Includes
MAX 7000AE
Altera Corporation
1
MAX 7000A
Programmable Logic
Device
October 2002, ver. 4.3
Data Sheet
DS-M7000A-4.3
Features...
High-performance 3.3-V EEPROM-based programmable logic
devices (PLDs) built on second-generation Multiple Array MatriX
(MAX
) architecture (see
Table 1
)
3.3-V in-system programmability (ISP) through the built-in
IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface with
advanced pin-locking capability
MAX 7000AE device in-system programmability (ISP) circuitry
compliant with IEEE Std. 1532
EPM7128A and EPM7256A device ISP circuitry compatible with
IEEE Std. 1532
Built-in boundary-scan test (BST) circuitry compliant with
IEEE Std. 1149.1
Supports JEDEC Jam Standard Test and Programming Language
(STAPL) JESD-71
Enhanced ISP features
Enhanced ISP algorithm for faster programming (excluding
EPM7128A and EPM7256A devices)
ISP_Done bit to ensure complete programming (excluding
EPM7128A and EPM7256A devices)
Pull-up resistor on I/O pins during in-system programming
Pin-compatible with the popular 5.0-V MAX 7000S devices
High-density PLDs ranging from 600 to 10,000 usable gates
Extended temperature range
f
For information on in-system programmable 5.0-V MAX 7000 or 2.5-V
MAX 7000B devices, see the
MAX 7000 Programmable Logic Device Family
Data Sheet
or the
MAX 7000B Programmable Logic Device Family Data Sheet
.
2
Altera Corporation
MAX 7000A Programmable Logic Device Data Sheet
...and More
Features
4.5-ns pin-to-pin logic delays with counter frequencies of up to
227.3 MHz
MultiVolt
TM
I/O interface enables device core to run at 3.3 V, while
I/O pins are compatible with 5.0-V, 3.3-V, and 2.5-V logic levels
Pin counts ranging from 44 to 256 in a variety of thin quad flat pack
(TQFP), plastic quad flat pack (PQFP), ball-grid array (BGA), space-
saving FineLine BGA
TM
, and plastic J-lead chip carrier (PLCC)
packages
Supports hot-socketing in MAX 7000AE devices
Programmable interconnect array (PIA) continuous routing structure
for fast, predictable performance
PCI-compatible
Bus-friendly architecture, including programmable slew-rate control
Open-drain output option
Programmable macrocell registers with individual clear, preset,
clock, and clock enable controls
Programmable power-up states for macrocell registers in
MAX 7000AE devices
Programmable power-saving mode for 50% or greater power
reduction in each macrocell
Configurable expander product-term distribution, allowing up to
32 product terms per macrocell
Programmable security bit for protection of proprietary designs
6 to 10 pin- or logic-driven output enable signals
Two global clock signals with optional inversion
Enhanced interconnect resources for improved routability
Fast input setup times provided by a dedicated path from I/O pin to
macrocell registers
Programmable output slew-rate control
Programmable ground pins
Table 1. MAX 7000A Device Features
Feature
EPM7032AE
EPM7064AE
EPM7128AE
EPM7256AE
EPM7512AE
Usable gates
600
1,250
2,500
5,000
10,000
Macrocells
32
64
128
256
512
Logic array blocks
2
4
8
16
32
Maximum user I/O
pins
36
68
100
164
212
t
PD
(ns)
4.5
4.5
5.0
5.5
7.5
t
SU
(ns)
2.9
2.8
3.3
3.9
5.6
t
FSU
(ns)
2.5
2.5
2.5
2.5
3.0
t
CO1
(ns)
3.0
3.1
3.4
3.5
4.7
f
CNT
(MHz)
227.3
222.2
192.3
172.4
116.3
Altera Corporation
3
MAX 7000A Programmable Logic Device Data Sheet
Software design support and automatic place-and-route provided by
Altera's development systems for Windows-based PCs and Sun
SPARCstation, and HP 9000 Series 700/800 workstations
Additional design entry and simulation support provided by EDIF
2 0 0 and 3 0 0 netlist files, library of parameterized modules (LPM),
Verilog HDL, VHDL, and other interfaces to popular EDA tools from
manufacturers such as Cadence, Exemplar Logic, Mentor Graphics,
OrCAD, Synopsys, Synplicity, and VeriBest
Programming support with Altera's Master Programming Unit
(MPU), MasterBlaster
TM
serial/universal serial bus (USB)
communications cable, ByteBlasterMV
TM
parallel port download
cable, and BitBlaster
TM
serial download cable, as well as
programming hardware from third-party manufacturers and any
Jam
TM
STAPL File (.jam), Jam Byte-Code File (.jbc), or Serial Vector
Format File- (.svf) capable in-circuit tester
General
Description
MAX 7000A (including MAX 7000AE) devices are high-density, high-
performance devices based on Altera's second-generation MAX
architecture. Fabricated with advanced CMOS technology, the EEPROM-
based MAX 7000A devices operate with a 3.3-V supply voltage and
provide 600 to 10,000 usable gates, ISP, pin-to-pin delays as fast as 4.5 ns,
and counter speeds of up to 227.3 MHz. MAX 7000A devices in the -4, -5,
-6, -7, and some -10 speed grades are compatible with the timing
requirements for 33 MHz operation of the PCI Special Interest Group (PCI
SIG) PCI Local Bus Specification, Revision 2.2. See
Table 2
.
Table 2. MAX 7000A Speed Grades
Device
Speed Grade
-4
-5
-6
-7
-10
-12
EPM7032AE
v
v
v
EPM7064AE
v
v
v
EPM7128A
v
v
v
v
EPM7128AE
v
v
v
EPM7256A
v
v
v
v
EPM7256AE
v
v
v
EPM7512AE
v
v
v
4
Altera Corporation
MAX 7000A Programmable Logic Device Data Sheet
The MAX 7000A architecture supports 100% transistor-to-transistor logic
(TTL) emulation and high-density integration of SSI, MSI, and LSI logic
functions. It easily integrates multiple devices including PALs, GALs, and
22V10s devices. MAX 7000A devices are available in a wide range of
packages, including PLCC, BGA, FineLine BGA, Ultra FineLine BGA,
PQFP, and TQFP packages. See
Table 3
and
Table 4
.
Notes to tables:
(1)
When the IEEE Std. 1149.1 (JTAG) interface is used for in-system programming or boundary-scan testing, four I/O
pins become JTAG pins.
(2)
All Ultra FineLine BGA packages are footprint-compatible via the SameFrame
TM
feature. Therefore, designers can
design a board to support a variety of devices, providing a flexible migration path across densities and pin counts.
Device migration is fully supported by Altera development tools. See
"SameFrame Pin-Outs" on page 15
for more
details.
(3)
All FineLine BGA packages are footprint-compatible via the SameFrame feature. Therefore, designers can design a
board to support a variety of devices, providing a flexible migration path across densities and pin counts. Device
migration is fully supported by Altera development tools. See
"SameFrame Pin-Outs" on page 15
for more details.
Table 3. MAX 7000A Maximum User I/O Pins
Note (1)
Device
44-Pin PLCC 44-Pin TQFP
49-Pin Ultra
FineLine
BGA
(2)
84-Pin PLCC
100-Pin
TQFP
100-Pin
FineLine
BGA
(3)
EPM7032AE
36
36
EPM7064AE
36
36
41
68
68
EPM7128A
68
84
84
EPM7128AE
68
84
84
EPM7256A
84
EPM7256AE
84
84
EPM7512AE
Table 4. MAX 7000A Maximum User I/O Pins
Note (1)
Device
144-Pin TQFP
169-Pin Ultra
FineLine BGA
(2)
208-Pin PQFP
256-Pin BGA
256-Pin FineLine
BGA
(3)
EPM7032AE
EPM7064AE
EPM7128A
100
100
EPM7128AE
100
100
100
EPM7256A
120
164
164
EPM7256AE
120
164
164
EPM7512AE
120
176
212
212
Altera Corporation
5
MAX 7000A Programmable Logic Device Data Sheet
MAX 7000A devices use CMOS EEPROM cells to implement logic
functions. The user-configurable MAX 7000A architecture accommodates
a variety of independent combinatorial and sequential logic functions.
The devices can be reprogrammed for quick and efficient iterations
during design development and debug cycles, and can be programmed
and erased up to 100 times.
MAX 7000A devices contain from 32 to 512 macrocells that are combined
into groups of 16 macrocells, called logic array blocks (LABs). Each
macrocell has a programmable-
AND
/fixed-
OR
array and a configurable
register with independently programmable clock, clock enable, clear, and
preset functions. To build complex logic functions, each macrocell can be
supplemented with both shareable expander product terms and high-
speed parallel expander product terms, providing up to 32 product terms
per macrocell.
MAX 7000A devices provide programmable speed/power optimization.
Speed-critical portions of a design can run at high speed/full power,
while the remaining portions run at reduced speed/low power. This
speed/power optimization feature enables the designer to configure one
or more macrocells to operate at 50% or lower power while adding only a
nominal timing delay. MAX 7000A devices also provide an option that
reduces the slew rate of the output buffers, minimizing noise transients
when non-speed-critical signals are switching. The output drivers of all
MAX 7000A devices can be set for 2.5 V or 3.3 V, and all input pins are
2.5-V, 3.3-V, and 5.0-V tolerant, allowing MAX 7000A devices to be used
in mixed-voltage systems.
MAX 7000A devices are supported by Altera development systems,
which are integrated packages that offer schematic, text--including
VHDL, Verilog HDL, and the Altera Hardware Description Language
(AHDL)--and waveform design entry, compilation and logic synthesis,
simulation and timing analysis, and device programming. The software
provides EDIF 2 0 0 and 3 0 0, LPM, VHDL, Verilog HDL, and other
interfaces for additional design entry and simulation support from other
industry-standard PC- and UNIX-workstation-based EDA tools. The
software runs on Windows-based PCs, as well as Sun SPARCstation, and
HP 9000 Series 700/800 workstations.
f
For more information on development tools, see the
MAX+PLUS II
Programmable Logic Development System & Software Data Sheet
and the
Quartus Programmable Logic Development System & Software Data Sheet
.
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