Document Outline
- Excalibur Device Overview Data Sheet version 2.0, May 2002
DS-EXCARM-2.0
Altera Corporation
1
Excalibur Device Overview
May 2002, ver. 2.0
Data Sheet
Features...
I
Combination of a world-class RISC processor system with industry-
leading programmable logic on a single device
I
Industry-standard ARM922T
TM
32-bit RISC processor core operating
at up to 200 MHz
ARMv4T instruction set with Thumb
extensions
Memory management unit (MMU) included for real-time
operating system (RTOS) support
Harvard cache architecture with 64-way set associative separate
8-Kbyte instruction and 8-Kbyte data caches
I
APEX
TM
20KE-like programmable logic architecture ranging from
100,000 to 1,000,000 gates (see
Table 1
on
page 3
)
I
Advanced bus architecture based on advanced microcontroller bus
architecture (AMBA
TM
) high-performance bus (AHB)
I
Embedded programmable on-chip peripherals
ETM9 embedded trace module to assist software debugging
Flexible interrupt controller
Universal asynchronous receiver/transmitter (UART)
General-purpose timer
Watchdog timer
I
Advanced memory support
Internal single-port SRAM up to 256 Kbytes
Internal dual-port SRAM up to 128 Kbytes
Internal SDRAM controller
-
Single data-rate (SDR) and double data-rate (DDR) support
-
Up to 512 Mbytes
-
Data rates to 133 (266) MHz
Expansion bus interface (EBI)
-
Compatible with industry-standard flash memory, SRAMs,
and peripheral devices
-
Four devices, each up to 32 Mbytes
I
PLD configuration/reconfiguration possible via the embedded
processor software
I
Fully configurable memory map
I
Extensive embedded system debug facilities
SignalTap
TM
embedded logic analyzer
ARM
JTAG processor debug support
Real-time data/instruction processor trace
Background debug monitoring via the IEEE Std. 1149.1 (JTAG)
interface
2
Altera Corporation
Excalibur Device Overview
I
Multiple and separate clock domains controlled by software-
programmable phased-lock loops (PLLs) for embedded
processor, SDRAM, and PLD
ClockBoost
TM
circuitry provides clock multiplication for the
embedded stripe and the PLD
ClockLock
TM
circuitry reduces clock delay and skew in the
PLD
I
Advanced packaging options (see
Tables 2
and
3
on
page 3
)
I
1.8-V supply voltage, but many I/O standards supported:
SSTL-3
LVTTL
GTL+
LVDS
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SOPC Builder system development tool
Intuitive graphical user interface (GUI) simplifies system
definition and customization
Wizard interface facilitates function customization for each
component
Automatically-generated logic integrates processors,
memories, peripherals, IP cores, on-chip buses and bus
arbiters
VHDL or Verilog HDL code created for system connection
Software develoment environment generated to match the
target hardware
I
Extended Quartus
TM
II development environment for Excalibur
TM
support
Integrated hardware and software development
environment
MegaWizard
Plug-In interface configures the embedded
processor, PLD, bus connections, and peripherals
C/C++ compiler, source-level debugger, and RTOS support
This document provides updated information about
Excalibur devices and should be used together with the
APEX 20K Programmable Logic Device Family Data Sheet.
Altera Corporation
3
Excalibur Device Overview
Note:
(1)
Maximum available user I/Os = shared stripe I/O + PLD I/O
Note to
Tables 2
and
3
:
(1)
I/O counts include dedicated input and clock pins.
Table 1. Excalibur Device Overview
Feature
EPXA1
EPXA4
EPXA10
Processor
ARM922T
ARM922T
ARM922T
Maximum operating frequency
200 MHz
200 MHz
200 MHz
Single-port SRAM
32 Kbytes
128 Kbytes
256 Kbytes
Dual-port SRAM
16 Kbytes
64 Kbytes
128 Kbytes
Typical gates
100,000
400,000
1,000,000
Logic elements (LEs)
4,160
16,640
38,400
Embedded system blocks (ESBs)
26
104
160
Maximum system gates
263,000
1,052,000
1,772,000
Maximum user I/Os
(1)
246
488
711
UART, timer, watchdog timer
Yes
Yes
Yes
JTAG debug module
Yes
Yes
Yes
Embedded trace module
Yes
Yes
General purpose I/O Port
4 bits
8 bits
-
Low-power PLL
Yes
-
-
Table 2. Excalibur Device FineLineTM BGA Package Sizes
Feature
FineLine BGA
484 Pin
672 Pin
1,020 Pin
Pitch (mm)
1.00
1.00
1.00
Area (mm
2
)
529
729
1,089
Length
Width (mm mm)
23
23
27
27
33
33
Table 3. Excalibur Device FineLine BGA Package Options & User I/O
Counts Note (1)
Device
FineLine BGA
484 Pin
672 Pin
1,020 Pin
EPXA1
186
246
EPXA4
426
488
EPXA10
711
4
Altera Corporation
Excalibur Device Overview
General
Description
Devices belonging to the Excalibur family combine an unparalleled
degree of integration and programmability. They offer an
outstanding embedded system development platform, providing a
cost-efficient access to leading-edge embedded processors and PLD
performance.
The Excalibur family offers a variety of PLD densities and memory
sizes to fit a wide range of applications and requirements. The high-
performance embedded architecture is ideal for compute-intensive
as well as high data-bandwidth applications.
Figure 1
shows the structure of the Excalibur devices. The embedded
stripe contains the processor core, peripherals, and memory
subsystem. The amounts of single- and dual-port memory vary as
listed in
Table 1 on page 3
.
Figure 2 on page 5
shows the system architecture of the embedded
stripe and the interfaces to the PLD portion of the devices. This
architecture promotes maximum integration with minimal system
cost and allows the embedded stripe and PLD to be independently
optimized for maximum performance.
Figure 1. Excalibur Architecture
PLL
Timer
UART
Interrupt
Controller
Watchdog
Timer
JT
A
G
128 Kbytes SRAM
64 Kbytes DPRAM
32 Kbytes SRAM
16 Kbytes DPRAM
256 Kbytes SRAM
128 Kbytes DPRAM
Embedded
Processor
Stripe
PLD
DPRAM
XA1
XA4
XA10
Trace
Module
ARM922T
SRAM
SRAM
SRAM
DPRAM
DPRAM
External
Memory
Interfaces
Altera Corporation
5
Excalibur Device Overview
Figure 2. Excalibur System Architecture
ARM922T
+ Cache
+ MMU
Interrupt
Controller
Watchdog
Timer
SDRAM
Controller
EBI
UART
AHB1-2
Bridge
Slave
Master
Slave
Master
Configu-
ration
Logic
Master
Single-
Port
SRAM 0
PLL
Reset
Module
Timer
PLD
PLD
Master(s)
Master(s)
Port A
Port B
User's Slave Modules in the PLD
Stripe Interface
AHB1
AHB2
Stripe-
To-
PLD
Bridge
PLD-
To-
Stripe
Bridge
PLD
External
Interface
Ports
Embedded Processor Stripe
Flash
ROM
SRAM
Slave
Slave
AHB
Master
Port
AHB
Slave
Port
User Modules Requiring
Direct Access to Large
Dual-Port or Single-Port RAMs
PLD Clock Domain(s)
AHB2 Clock Domain
Processor Clock Domain (AHB1)
Master
Master
Dual-
Port
Port
SRAM 0
SRAM 0
Bus Control
SDRAM Clock Domain
SDRAM
Used for dual-port SRAM with dedicated
PLD access (no access to AHB1 and
AHB2)
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