Document Outline
- FLEX 10K Programmable Logic Family Data Sheet
Altera Corporation
1
FLEX 10K
Embedded Programmable
Logic Family
May 1998, ver. 3.10
Data Sheet
A-DS-F10K-03.10
Features...
s
The industrys first embedded programmable logic device (PLD)
family, providing system integration in a single device
Embedded array for implementing megafunctions, such as
efficient memory and specialized logic functions
Logic array for general logic functions
s
High density
10,000 to 250,000 typical gates (see Tables 1 and 2)
Up to 40,960 RAM bits; 2,048 bits per embedded array block
(EAB), all of which can be used without reducing logic capacity
s
System-level features
MultiVolt
I/O interface support
5.0-V tolerant input pins in FLEX
10KA devices
Low power consumption (typical specification less than 0.5 mA
in standby mode for most devices)
FLEX 10K and FLEX 10KA devices support peripheral
component interconnect Special Interest Groups (PCI-SIG)
PCI
Local Bus Specification, Revision 2.1
FLEX 10KA devices include pull-up clamping diode, selectable
on a pin-by-pin basis for 3.3-V PCI compliance
Built-in JTAG boundary-scan test (BST) circuitry compliant with
IEEE Std. 1149.1-1990, available without consuming any device
logic
Table 1. FLEX 10K Device Features
Feature
EPF10K10
EPF10K10A
EPF10K20
EPF10K30
EPF10K30A
EPF10K40
EPF10K50
EPF10K50V
Typical gates (logic and RAM),
Note (1)
10,000
20,000
30,000
40,000
50,000
Usable gates
7,000 to
31,000
15,000 to
63,000
22,000 to
69,000
29,000 to
93,000
36,000 to
116,000
Logic elements (LEs)
576
1,152
1,728
2,304
2,880
Logic array blocks (LABs)
72
144
216
288
360
Embedded array blocks (EABs)
3
6
6
8
10
Total RAM bits
6,144
12,288
12,288
16,384
20,480
Maximum user I/O pins
134
189
246
189
310
2
Altera Corporation
FLEX 10K Embedded Programmable Logic Family Data Sheet
Note to tables:
(1)
For designs that require JTAG boundary-scan testing, the built-in JTAG circuitry contributes up to 31,250 additional
gates.
...and More
Features
Devices are fabricated on advanced processes and operate with
a 3.3- or 5.0-V supply voltage (see Table 3)
In-circuit reconfigurability (ICR) via external Configuration
EPROM, intelligent controller, or JTAG port
ClockLock and ClockBoost options for reduced clock
delay/skew and clock multiplication
Built-in low-skew clock distribution trees
100
%
functional testing of all devices; test vectors or scan chains
are not required
Table 2. FLEX 10K Device Features
Feature
EPF10K70
EPF10K100
EPF10K100A
EPF10K130V
EPF10K250A
Typical gates (logic and
RAM),
Note (1)
70,000
100,000
130,000
250,000
Usable gates
46,000 to 118,000
62,000 to 158,000
82,000 to 211,000
149,000 to
310,000
LEs
3,744
4,992
6,656
12,160
LABs
468
624
832
1,520
EABs
9
12
16
20
Total RAM bits
18,432
24,576
32,768
40,960
Maximum user I/O pins
358
406
470
470
Table 3. Supply Voltages
Feature
FLEX 10K Devices
FLEX 10KA Devices
EPF10K10
EPF10K20
EPF10K30
EPF10K40
EPF10K50
EPF10K70
EPF10K100
EPF10K10A
EPF10K30A
EPF10K50V
EPF10K100A
EPF10K130V
EPF10K250A
Supply voltage (V
CCINT
)
5.0 V
3.3 V
Altera Corporation
3
FLEX 10K Embedded Programmable Logic Family Data Sheet
s
Flexible interconnect
FastTrack Interconnect continuous routing structure for fast,
predictable interconnect delays
Dedicated carry chain that implements arithmetic functions such
as fast adders, counters, and comparators (automatically used by
software tools and megafunctions)
Dedicated cascade chain that implements high-speed, high-fan-
in logic functions (automatically used by software tools and
megafunctions)
Tri-state emulation that implements internal tri-state buses
Up to six global clock signals and four global clear signals
s
Powerful I/O pins
Individual tri-state output enable control for each pin
Open-drain option on each I/O pin
Programmable output slew-rate control to reduce switching
noise
s
Peripheral register for fast setup and clock-to-output delay
s
Flexible package options
Available in a variety of packages with 84 to 600 pins (see
Table 4)
Pin-compatibility with other FLEX 10K devices in the same
package
s
Software design support and automatic place-and-route provided by
Alteras MAX+PLUS
II development system for 486- and Pentium-
based PCs and Sun SPARCstation, HP 9000 Series 700/800, and IBM
RISC System/6000 workstations
s
Additional design entry and simulation support provided by EDIF
2 0 0 and 3 0 0 netlist files, library of parameterized modules (LPM),
DesignWare components, Verilog HDL, VHDL, and other interfaces
to popular EDA tools from manufacturers such as Cadence,
Exemplar Logic, Mentor Graphics, OrCAD, Synopsys, Synplicity,
VeriBest, and Viewlogic
4
Altera Corporation
FLEX 10K Embedded Programmable Logic Family Data Sheet
Notes:
(1)
Contact Altera Customer Marketing for up-to-date information on package availability.
(2)
FLEX 10K device package types include plastic J-lead chip carrier (PLCC), thin quad flat pack (TQFP), plastic quad
flat pack (PQFP), power quad flat pack (RQFP), ball-grid array (BGA), and pin-grid array (PGA) packages.
General
Description
Alteras FLEX 10K devices are the industrys first embedded PLDs. Based
on reconfigurable CMOS SRAM elements, the Flexible Logic Element
MatriX (FLEX) architecture incorporates all features necessary to
implement common gate array megafunctions. With up to 250,000 gates,
the FLEX 10K family provides the density, speed, and features to integrate
entire systems, including multiple 32-bit buses, into a single device.
FLEX 10K devices are configurable, and they are 100
%
tested prior to
shipment. As a result, the designer is not required to generate test vectors
for fault coverage purposes. Instead, the designer can focus on simulation
and design verification. In addition, the designer does not need to manage
inventories of different gate array designs; FLEX 10K devices can be
configured on the board for the specific functionality required.
Table 5 shows FLEX 10K performance for some common designs. All
performance values shown were obtained with Synopsys DesignWare or
LPM functions. No special design technique is required to implement the
applications; the designer simply infers or instantiates a function in a
Verilog HDL, VHDL, Altera Hardware Description Language (AHDL), or
schematic design file.
Table 4. FLEX 10K Package Options & I/O Pin Count
Notes (1), (2)
Device
84-Pin
PLCC
144-Pin
TQFP
208-Pin
PQFP
RQFP
240-Pin
PQFP
RQFP
256-Pin
BGA
356-Pin
BGA
403-Pin
PGA
503-Pin
PGA
599-Pin
PGA
600-Pin
BGA
EPF10K10
59
102
134
EPF10K10A
102
134
EPF10K20
102
147
189
EPF10K30
147
189
246
EPF10K30A
102
147
189
189
EPF10K40
147
189
EPF10K50
189
274
310
EPF10K50V
189
274
EPF10K70
189
358
EPF10K100
406
EPF10K100A
189
274
406
EPF10K130V
470
470
EPF10K250A
470
470
Altera Corporation
5
FLEX 10K Embedded Programmable Logic Family Data Sheet
Notes:
(1)
The speed grade of this application is limited because of clock high and low specifications.
(2)
This application uses combinatorial inputs and outputs.
(3)
This application uses registered inputs and outputs.
The FLEX 10K architecture is similar to that of embedded gate arrays, the
fastest-growing segment of the gate array market. As with standard gate
arrays, embedded gate arrays implement general logic in a conventional
sea-of-gates architecture. In addition, embedded gate arrays have
dedicated die areas for implementing large, specialized functions. By
embedding functions in silicon, embedded gate arrays provide reduced
die area and increased speed compared to standard gate arrays. However,
embedded megafunctions typically cannot be customized, limiting the
designers options. In contrast, FLEX 10K devices are programmable,
providing the designer with full control over embedded megafunctions
and general logic while facilitating iterative design changes during
debugging.
Each FLEX 10K device contains an embedded array and a logic array. The
embedded array is used to implement a variety of memory functions or
complex logic functions, such as digital signal processing (DSP),
microcontroller, wide-data-path manipulation, and data-transformation
functions. The logic array performs the same function as the sea-of-gates
in the gate array: it is used to implement general logic, such as counters,
adders, state machines, and multiplexers. The combination of embedded
and logic arrays provides the high performance and high density of
embedded gate arrays, enabling designers to implement an entire system
on a single device.
Table 5. FLEX 10K Performance
Application
Resources
Used
Performance
Units
LEs
EABs -1 Speed Grade -2 Speed Grade -3 Speed Grade -4 Speed Grade
16-bit loadable
counter,
Note (1)
16
0
204
166
125
95
MHz
16-bit accumulator,
Note (1)
16
0
204
166
125
95
MHz
16-to-1 multiplexer,
Note (2)
10
0
4.5
5.8
6.0
7.0
ns
256
8 RAM read
cycle speed,
Note (3)
0
1
185
118
103
84
MHz
256
8 RAM write
cycle speed,
Note (3)
0
1
106
86
77
63
MHz
PDF 
ZIP