1
EV2060
GIGABIT ETHERNET TRANSCEIVER EVALUATION BOARDS
REVISION 4.0
May 9, 2000
EV2060
GIGABIT ETHERNET TRANSCEIVER EVALUATION BOARDS
REVISION 4.0
EVALUATION BOARD OVERVIEW
This document describes operation and usage of the S2060 evaluation boards. The evaluation boards allow
users to become familiar with the functionality of the S2060 Gigabit Ethernet Transceiver. Specifically, Bit Error
Rate (BER), jitter, and basic performance can be tested using the evaluation boards. This document provides a
complete board description, explains various test configurations, and contains a bill of materials with a corre-
sponding schematic. This document should be used in conjunction with the S2060 data sheet and application
note. Figure 1 shows an outline of the S2060A evaluation board.
Figure 1. S2060 Evaluation Board
GND
A
A
A
B
C
D
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A
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2
EV2060
GIGABIT ETHERNET TRANSCEIVER EVALUATION BOARDS
REVISION 4.0
May 9, 2000
EVALUATION BOARD DESCRIPTION
This section describes the functionality of the connectors and settings recommended for the S2060 evaluation
boards. Brief descriptions of the SMA connectors on board, dip switch descriptions and settings, power and
grounds, output levels, header settings, and probes are presented. The letters "A", "B", "C", and "D" correspond
to specific parts on the evaluation board shown in Figure 1, and are described in the following section according
to their letter designation in Figure 1.
[A] SMA Connectors
SMA connectors are provided for the differential serial data input/output signals and output clock. Additional
SMA connectors are provided for an optional differential serial input clock, the external TTL reference clock and
the optional external parallel input clock. Table 1 gives a description of the SMA connectors.
Table 1. SMA Connectors
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Table 2. Dip Switch Functional Description
[B] Dip Switches
The evaluation board is equipped with a DIP switch to control the static control functions of the on-board
devices. For both arrays the OFF (open = "0") condition of the DIP switch asserts a logic low on the assigned
signal, and the ON (closed = "1") condition asserts a logic high. Note that "0" and "1" are printed on the
evaluation board. Table 2 shows the functional DIP switch descriptions. Table 3 shows DIP switch settings
corresponding to the tests described at the end of this document.
3
EV2060
GIGABIT ETHERNET TRANSCEIVER EVALUATION BOARDS
REVISION 4.0
May 9, 2000
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Table 3. Dip Switch Settings for Test and Evaluation Configurations
Table 4. S2060 Power and Ground Values
VOH
VOL
Termination = 50
to (VCC-2V)
or 150
to VEE
Vcc -1.3 V (internal
DC bias point)
Figure 2. Single-Ended LVPECL Output Swing
[C] Power/Ground
Three terminal outputs are provided at the top edge of the board for Vcc and Vee. The S2060 is specified for 3.3
V +/- 5%.
The TXP/N single-ended LVPECL output swing is shown in Figure 2. The bias point is internally set 1.3 volts
below the Vcc rail. As discussed in both the S2060 data sheet and application note, 150
pulldown resistors are
recommended on the positive and negative outputs for full output voltage swing. Test equipment inputs, how-
ever, typically provide 50
loads. When interfacing to test equipment the Vcc and Vee input levels may be
shifted to 2.0 V and 1.3 V respectively in order to maintain full voltage swing with the smaller load. Table 4
summarizes the voltage rail settings and associated output loading.
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4
EV2060
GIGABIT ETHERNET TRANSCEIVER EVALUATION BOARDS
REVISION 4.0
May 9, 2000
Table 5. Evaluation Board Header Descriptions
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[D] Probes (Headers)
RCB1, RCB0, and COM_DET are probe points. The output levels of RCB1, RCB0, and COM_DET pins can be
probed during testing. These pins must be left unjumpered.
RX[0:9], TX[0:9] and GND can be either jumpered, utilized as probe points, or utilized as active I/O. RX[0:9] and
TX[0:9] can be jumpered such that parallel output (RX[0:9] ) is bridged directly to the parallel input (TX[0:9]).
Selected RX[0:9] and TX[0:9] pins can also be jumpered to ground to set up a static input configuration. The
probe descriptions are given in Table 5. DUT input and output signals are typically routed to and from the
evaluation board through the serial I/O. Providing evaluation board I/O through the parallel connectors would
require the user to construct a cable harness.
5
EV2060
GIGABIT ETHERNET TRANSCEIVER EVALUATION BOARDS
REVISION 4.0
May 9, 2000
SCHEMATIC/BILL OF MATERIALS
Figures 3 and 4 provide a schematic representation of the evaluation boards. Table 6 lists the Bill of Materials for
the evaluation boards.
Figure 3. Signal Connections
Figure 4. Power and Ground Connections
S2060
C1
R2
R1
R4
R2
R3
R3
RX9
RX0
REFCLKP
RXN
RXP
SMA
SMA
TXP
TXN
RBC0
RBC1
COM-DET
TX0
TX9
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EN_CDET
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C1
C1
21
25
32
47
56
58
64
15
51
5
21
10
20
23
37
42
55
60
18
50
L
L
L
L
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Vcc
S2060
C3
C1
C2
C1
C2
C1
C2
C1
C2
C1
C2
C1
C2
C1
C2
C1
C2
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