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EV3032
SONET/SDH/ATM OC-12 TRANSCEIVER EVALUATION BOARD
September 22, 1999
EV3032
SONET/SDH/ATM OC-12 TRANSCEIVER EVALUATION BOARD
Description
The S3032 evaluation board provides a flexible platform for verifying the operation of the S3032 transceiver
interface circuit. This document provides information on the board contents. It should be used in conjunction with
the S3032 data sheet, which contains full technical details on the chips operation.
Figure 1 shows the outline of the S3032 evaluation board. Figure 2 shows the block diagram of how the S3032
evaluation board should be connected to test equipment for Bit Error Rate (BER) testing. Figure 3 shows the test
setup for the BER measurements and jitter testing.
Figure 1. S3032 Evaluation Board Top View
GND
RSDP
RSDN
TSCLKP
TSCLKN
TSDN
TSDP
DUT
VEE
GND
DUT
VCC
REFCLKP
REFCLKN
TTLREF
POCLK
PCLK
PICLK
PIN7
PIN6
PIN5
PIN4
PIN3
PIN2
PIN1
PIN0
GND
POUT7:0
PIN7:0
GND
OPEN
FOR NC
FP
GND
RSTB
(MODE JUMPERS)
GND
"1"
"0"
LLEB
SDPECL
DLEB
OOF
TESTEN
MODE1
MODE0
SLPTIME
"1"
"0"
AMCC
6290 SEQUENCE DR.
SAN DIEGO, CA 92121
APPLIED MICRO CIRCUITS CORPORATION
S3032 SONET/SDH/ATM 0C-3/12 TRANSCEIVER WITH CDR
S3032
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SONET/SDH/ATM OC-12 TRANSCEIVER EVALUATION BOARD
EV3032
September 22, 1999
Figure 2. S3032 Bit Error Rate (BER) Test Setup
Figure 2 depicts how the S3032 evaluation board can be connected for BER measurements, and shows all of
the DIP switch settings and the Level Shifted ECL (LSECL) power supply requirements for use with test
equipment that utilizes 50
to ground termination. In this configuration the S3032 is configured for use with the
internal S3032 Clock Recovery Unit (CRU), using a 19.44 MHz reference and operating at STS-12.
S3032 DUT
BERT TX (622MHz)
RSDP
RSDN
TSDP
TSDN
TSCLKP
TSCLKN
REFCLKP
REFCLKN
TTLREF
HP8133 PULSE
GENERATOR OR DIVIDER
BERT RX
DATA
CLOCK
DATA
CLOCK
DATA
DATA
CLOCK
EXT IN
OUT
(DIV BY 32)
OUT
S3032 BER
TEST
19.44MHz
+2v
POWER SUPPLY
DUT VCC = +2V
DUT VEE = -1.3v +/- 5%
GND = 0V
DIP SWITCH SETTINGS:
LLEB '1'
SDPECL '1'
DLEB '1'
OOF '0'
MODE1 '0'
MODE0 '0'
SLPTIME '0'
FOR example
19.44MHz operation
622MHz
LSECL CONFIGURATION
50 ohm
or not
connected
+1.2V
+0.2V
+0.7V
10K
TESTEN '0'
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EV3032
SONET/SDH/ATM OC-12 TRANSCEIVER EVALUATION BOARD
September 22, 1999
Figure 3. S3032 BER Measurement and Jitter Test Setup
DATA
CLOCK
DATA
DATA
CLOCK
TSCLKN
THRU DATA
REFCLK
DATA OUTPUT
RSDP
RSDN
PIN 0
PIN 1
PIN 2
PIN 3
PIN 4
PIN 5
PIN 6
PIN 7
PICLK
POUT 0
POUT 1
POUT 2
POUT 3
POUT 4
POUT 5
POUT 6
POUT7
POCLK
Trigger
MEASURE DATA EYE
Scope
FF00 HEX OR PRBS PATTERN
2
7
-1 PRBS
BERT RX(622.08MHz)
TEKTRONIX JITTER ANALYZER
SJ300 (622.08MHz)
INPUT CLOCK
MEASURE JITTER
GENERATION
EXT IN
BERT TX (622.08MHz)
CLOCK CLOCK
S3032 DUT(TX)
S3032
DUT(RX)
OUT
OUT
(DIVIDE BY 32)
EXT CLK (155.52MHz)
HP8133 OR DIVIDER
LVECL
BUFFER
POWER DIVIDERS
CASCADE MICROTECH ECL
TERMINATOR
VTT=-2.45V
REFCLKN
REFCLKP
REFCLKP REFCLKN
TSDP
TSCLKP
RSDP
RSDN
TSDN
DATA
-3.3V
TTL BUS
BERT TX(622.08MHz)
JITTERED
OUTPUT
2
7
-1 PRBS DATA PATTERN
-3.3V
-3.3V
DUT VCC = 0V
DUT VEE = -3.3V +/- 5%
LLEB '1'
SDPECL '1'
DLEB '1'
OOF '0'
TESTEN '0'
MODE1 '0'
MODE0 '0'
SLPTIME '0'
FOR 19.44MHz
OPERATION
VIH = -0.8
ECL INPUT LEVEL
FOR ALL
VIL = -1.8
DIP SWITCH
SETTING
NOTE: At low frequency (10-30Hz)
the reference clock must be Jittered
Provides Asynchronous Data
Figure 3 depicts how two S3032 evaluation boards can be connected for BER measurements and jitter testing,
and shows all of the DIP switch settings and the power supply requirements for use with test equipment that
utilizes 50
to -2V termination. The DIP switch settings are for STS-12 testing.
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SONET/SDH/ATM OC-12 TRANSCEIVER EVALUATION BOARD
EV3032
September 22, 1999
Table 1. Power Connections for DUT and Test Equipment Interface
ELECTRICAL CONNECTIONS
Power Connections
Terminal posts are provided at the top edge of the board for VCC and VEE. The S3032 evaluation board can be
configured with ECL, PECL and Level Shifted (LSECL) I/O so the board can be configured to operate with
different types of standard test equipment. Figures 4 through 6 demonstrate the different types of input and
output waveforms that the S3032 evaluation board can operate with the different voltage settings of VCC and
VEE per Table 1. Note the TTL I/O's voltage level will change to non-standard levels when the S3032 evaluation
board is powered by the different voltage.
The external test equipment environment or other standard ECL and/or +3.3V referenced ECL systems can
interface to the S3032 evaluation board. The board as shown in Figures 1 through 3 can be powered to allow
easy connection to the 50
to ground inputs of high performance oscilloscopes and spectrum analyzers as well
as the standard ECL I/O of serial Bit Error Rate Testers (BERT) and jitter analyzers. Table 1 illustrates the
nominal input voltages for DUT VCC and VEE voltage levels shown in Figures 4 through 6. Figures 4 and 5
show that the voltages track with VEE, and Figure 6 shows that the voltages track with VCC.
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EV3032
SONET/SDH/ATM OC-12 TRANSCEIVER EVALUATION BOARD
September 22, 1999
Figure 4. LVECL Signal Waveform
Figure 6. LVPECL Signal Waveform
Figure 5. LSECL Signal Waveform
VCC = 0V
-0.8V
-1.3V
-1.8V
Termination = 50
to -2V
VEE = -3.3V +/- 5%
LVECL
Termination = 50
to GND
LSECL
VCC = +2V
+1.2V
+0.7V
+0.2V
VEE = -1.3V +/- 5%
LVPECL
VCC = +3.3V +/- 5%
2.5V
2V
1.5V
VEE = 0V
Termination = 50
to (VCC -2V)
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