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EV3037QF
SONET/SDH/ATM STS-12 TRANSCEIVER EVALUATION BOARD
July 2, 1999
EV3037QF
DESCRIPTION
The S3037 Evaluation Board provides a flexible platform for verifying the operation of the S3037 transceiver
interface circuit. This data sheet provides information on the board contents. It should be used in conjunction
with the S3037 data sheet, which contains full technical details on chip operation.
Figure 1 shows the outline of the S3037 Evaluation Board, and Figure 2 shows the block diagram of how the
S3037 Evaluation Board should be connected to test equipment for BER testing. In this configuration the S3037
is configured for use with the internal S3037 Clock Recovery Unit (CRU), using a 19.44 or 77.76 MHz reference
and operating at STS-12.
SONET/SDH/ATM STS-12 TRANSCEIVER EVALUATION BOARD
Figure 1.
DUT
VEE
GND DUT
VCC
A
MCC
6290 SEQUENCE DRIVE
SAN DIEGO, CA 92121
S3037 SONET/SDH/ATM OC-12 Transceiver w/ CDR
MODE1
MODE0
SLPTIME
"1"
"0"
2 3 4
1
OOF
6 7
5
SDPECL
LLEB
DLEB
RSDP
RSDN
TSDP
TSDN
GND
GND
REFCLKP
REFCLKN
TTLREF
GND
GND
FP
R
RSTB
8
TESTEN
POCLK
PCLK
GND
PIN7:0
POUT7:0
GND
AMCC
S3037
PIN0
PICLK
PIN7
PIN6
PIN5
PIN4
PIN3
PIN2
PIN1
NC
2
SONET/SDH/ATM STS-12 TRANSCEIVER EVALUATION BOARD
EV3037QF
July 2, 1999
Figure 2 depicts how the S3037 Evaluation Board can be connected for BER measurements, and shows all of
the dip switch settings and the LVPECL power supply requirements for use with test equipment that utilizes 50
ohms to ground termination.
Figure 2.
TSDP
TSDN
RSDP
RSDN
PCLK
S3037
DIPSWITCH
REFCLK
P
TTLREF
REFCLKN
DUTVEE
DUTVCC
GND
PICLK
POCLK
PIN7
POUT7
PIN1
PIN2
PIN3
PIN4
PIN5
PIN6
PIN0
POUT0
POUT1
POUT2
POUT3
POUT4
POUT5
POUT6
RSTB
DATAN
CLOCKP
DATAP
CLOCKN
HP 70841B
CLOCK IN
-2v
DATA IN
-2v
P
A
TTERN GENERA
T
O
R
622.08Mhz
ERROR
DETECT
OR
HP 70842B
OUTP
EXT IN
/32
OUTN
HP 8133A
PULSE
GENERATOR
ECL
TERM.
TRIG OUT
(PATTERN)
CH.1
CH.2
TRIG
DSO TEK
11801A
SWITCH SETTINGS
LLEB=1
DLEB=1
SDPECL=1
OOF=0
TESTEN=0
MODE1=0
MODE0=0
SLPTIME=0
DUT VEE = -3.3V
GND = 0V
DUT VCC = 0V
S3037 SET UP FOR NORMAL OPERATION
CLK=622.08Mhz, REFCLK=19.44Mhz
HIGH = -800mV
LOW = -1.6V
3
EV3037QF
SONET/SDH/ATM STS-12 TRANSCEIVER EVALUATION BOARD
July 2, 1999
Figure 3 depicts how two S3037 Evaluation boards can be connected for jitter generation testing, and shows all
of the dip switch settings and the power supply requirements for use with test equipment that utilizes 50 ohms to
-2V termination. These settings are for STS-12 testing.
Figure 3.
TSDP
TSDN
RSDP
RSDN
PCLK
S3037
DIPSWITCH
REFCLK
P
TTLREF
REFCLKN
DUTVEE
DUTVCC
GND
PICLK
POCLK
PIN7
POUT7
PIN1
PIN2
PIN3
PIN4
PIN5
PIN6
PIN0
POUT0
POUT1
POUT2
POUT3
POUT4
POUT5
POUT6
RSTB
DATAN
CLOCKP
DATAP
CLOCKN
HP 70841B
CLOCK IN
-2v
DATA IN
-2v
P
A
TTERN GENERA
T
O
R
622.08Mhz
ERROR
DETECT
OR
HP 70842B
OUTP
EXT IN
/32
OUTN
HP 8133A
PULSE
GENERATOR
TRIG OUT
(PATTERN)
DA
T
AIN
MICROWAVE LOGIC
SJ-300
SWITCH SETTINGS
LLEB=1
DLEB=1
SDPECL=1
OOF=0
TESTEN=0
MODE1=0
MODE0=0
SLPTIME=0
DUT VEE = -3.3V
GND = 0V
DUT VCC = 0V
S3037 SET UP FOR JITTER GENERATION
CLK=622.08Mhz, REFCLK=19.44Mhz
HIGH = -800mV
LOW = -1.6V
4
SONET/SDH/ATM STS-12 TRANSCEIVER EVALUATION BOARD
EV3037QF
July 2, 1999
Figure 4 depicts how two S3037 Evaluation boards can be connected for jitter transfer testing, and shows all of
the dip switch settings and the power supply requirements for use with test equipment that utilizes 50 ohms to
-2V termination. These settings are for STS-12 testing.
Figure 4.
TSDP
TSDN
RSDP
RSDN
PCLK
S3037
DIPSWITCH
REFCLK
P
TTLREF
REFCLKN
DUTVEE
DUTVCC
GND
PICLK
POCLK
PIN7
POUT7
PIN1
PIN2
PIN3
PIN4
PIN5
PIN6
PIN0
POUT0
POUT1
POUT2
POUT3
POUT4
POUT5
POUT6
RSTB
DATAN
CLOCKP
DATAP
CLOCKN
HP 70841B
CLOCK IN
-2v
DATA IN
-2v
P
A
TTERN GENERA
T
O
R
622.08Mhz
ERROR
DETECT
OR
HP 70842B
OUTP
EXT IN
/32
OUTN
HP 8133A
PULSE
GENERATOR
TRIG OUT
(PATTERN)
DA
T
AIN
MICROWAVE LOGIC
SJ-300
SWITCH SETTINGS
LLEB=1
DLEB=1
SDPECL=1
OOF=0
TESTEN=0
MODE1=0
MODE0=0
SLPTIME=0
DUT VEE = -3.3V
GND = 0V
DUT VCC = 0V
S3037 SET UP FOR JITTER TRANSFER/TOLERANCE
CLK=622.08Mhz, REFCLK=19.44Mhz
HIGH = -800mV
LOW = -1.6V
EXT
RefCLK
THRU
D
ATA
DA
T
A
OUT
ECL BOARD
VEE = -5V
5
EV3037QF
SONET/SDH/ATM STS-12 TRANSCEIVER EVALUATION BOARD
July 2, 1999
ELECTRICAL CONNECTIONS
Power Connections
Terminal posts are provided at the top edge of the board for V
CC
and V
EE
. The S3037 Evaluation Board can be
configured with PECL and Level Shifted (LSECL) I/O so the board can be configured to operate with different
types of standard test equipment. Figures 5 through 7 demonstrate the different types of input and output
waveforms that the S3037 Evaluation Board can output with the different voltage settings of V
CC
and V
EE
per
Table 1. Note the TTL I/O's voltage level will change to non-standard levels when the S3037 Evaluation Board is
powered by the different voltage.
LVPECL
VCC = +3.3V
5%
2.5V
2V
1.5V
VEE = 0V
Termination = 50 Ohms to (VCC -2V)
Figure 5.
Figure 6.
Figure 7.
LVECL
VCC = 0V
-0.8V
-1.3V
-1.8V
VEE = 3.3V
5%
Termination = 50 Ohms to -2V
LSECL
VCC = +2V
+1.2V
+0.7V
+0.2V
VEE = -1.3V
5%
Termination = 50 Ohms to GND
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