1
EV3040
OC-48 CLOCK RECOVERY UNIT EVALUATION BOARD
August 13, 1999
EV3040
OC-48 CLOCK RECOVERY UNIT EVALUATION BOARD
DESCRIPTION
The S3040 evaluation board provides a flexible plat-
form for verifying the operation of AMCC OC-48
clock recovery units. This document provides infor-
mation on the board contents and layout. It should
be used in conjuction with the S3040 data sheet,
which contains full technical details on the chips op-
eration.
The S3040 evaluation board is factory configured
with the S3040 device, and includes a test point to
monitor the LOCKDET output. The board can be
configured with either the on-board ECL crystal os-
cillator or with an external oscillator connected via
the REFCLKP/N connectors.
Power Connections
Terminal posts are provided at the top edge of the
board allowing separate control of voltage levels for
the S3040 itself. The serial input is terminated on the
chip, and capacitive bypass to ground is provided on
the board. For operation with standard test equip-
ment, the board should be operated below ground,
with the VEE supply at -5V DC.
Figure 1. Evaluation Board Top View
SERCLKON
OFF
1
2
3
4
SERCLKOP
SERDATON
SERDATOP
GND S3040
VEE (-5V)
LOCKDET
GND
LCKREFN
REFCLKN
REFCLKP
ECL CRYSTAL
OSCILLATOR (option)
(on back)
SDN
BYPASS
NC
GND
0.01
0.01
GND
1.0K
SERDATIN
SERDATIP
S3040
ELECTRICAL CONNECTIONS
2
EV3040
OC-48 CLOCK RECOVERY UNIT EVALUATION BOARD
August 13, 1999
SET-UP FOR JITTER MEASUREMENT
Figure 2 depicts how the S3040 evaluation board can be connected for jitter measurements, and shows all of the
DIP switch settings and power supply requirements. The connection from A to B will be used for the PK-PK jitter
generation measurement on the Digital Sampling Oscilloscope (DSO). The connection from A to C will be used
for the jitter transfer, jitter tolerance and jitter generation measurement on the transition analyzer.
HP 70841B
B.E.R.T.
Tx (2.488 GHz)
S3040
HP 70842B
B.E.R.T.
Rx (2.488 GHz)
HP 70820A
Transition Analyzer
Tek CSA 803
D.S.O.
HP 3325
HP 8624B
BUFFER
SERDATIP
SERDATIN
CLK P
CLK N
MODULATION
INPUT
INPUT : 2
INPUT : 1
HP pn# 0955-0731
HP pn# 0955-0731
SERCLKOP
SERCLKON
SERDATOP
SERDATON
REFCLK
155.52 MHz
A
B
C
REFCLKP
REFCLKN
MAIN SIGNAL
CONNECTION
MEASUREMENT
A B :
PK-PK JITTER
A C :
JITTER TRANSFER
JITTER TOLERANCE
JITTER GENERATION
DIP SWITCH
LCKREFN
SDN
BYPASS
NOT USED
DIP SETTINGS
HI
LO
LO
N/A
HI (0V)
LCK/DATA
DATA OUT/OFF
VCO/OFF
N/A
LO (-5.0V)
LCK/REF
DATA OUT/ON
VCO/ON
N/A
POWER
VCC=GND :0V
VEE : -5.0V
Bandpass filter
2.488 GHz
Bandpass filter
2.488 GHz
Figure 2. Jitter Test Setup
3
EV3040
OC-48 CLOCK RECOVERY UNIT EVALUATION BOARD
August 13, 1999
y
l
p
p
u
S
r
e
w
o
P
t
u
p
n
I
l
a
n
i
m
o
N
e
g
a
t
l
o
V
l
a
n
g
i
S
f
o
e
p
y
T
t
u
p
t
u
O
L
M
C
n
o
i
t
a
n
i
m
r
e
T
C
C
V
T
U
D
E
E
V
T
U
D
V
0
V
0
.
5
-
L
C
E
0
5
D
N
G
o
t
Table 1. Power Connections for DUT and Test Equipment Interface
SMA Connectors
SMA connectors are provided for the differential serial data input/output signals and output clock.
Serial Data In [SERDATIP/N] PECL Differential inputs. Clock is recovered from the transition on these inputs.
Reference Clock [REFCLKP/N] PECL Differential inputs. These inputs are used to establish the initial
operating frequency of the clock recovery PLL and are also used as a standby clock in the absence of data.
These inputs must be provided with a differential clock of 155.52 MHz.
Serial Data Out [SERDATOP/N] CML outputs. This signal is the delayed version of the incoming data stream
(SERDATI) updated on the falling edge of Serial Clock Out (SERCLKOP).
Serial Clock Output [SERCLKP/N] CML outputs. This signal is phase aligned with Serial Data Out
(SERDATOP).
Lock Detect [LOCKDET] TTL output. Indicates that the Clock Recovery Unit (CRU) has locked onto the
incoming data stream.
DIP Switches
The evaluation board is equipped with a DIP switch to control the static control functions of the on-board device.
For both arrays the OFF (open = "0") condition of the DIP switch asserts a logic low on the assigned signal, and
the ON (closed = "1") condition asserts a logic high. Figure 2 shows the particular DIP switch settings that are
needed for a particular test case.
Lock to Reference [LCKREFN] Active Low. When active, the serial clock output will be forced to lock to the
local reference clock input [REFCLK].
Signal Detect [SDN] Active Low. Used to indicate a loss of received optical power.
Bypass Enable [BYPASS] Active High. Used to bypass the VCO in the PLL.
4
EV3040
OC-48 CLOCK RECOVERY UNIT EVALUATION BOARD
August 13, 1999
1
OUTN
2
VEE
3
OUTP
4
VCC
Y1
OSCECL
J4
J3
GND
C6 .1uf
C7 .1uf
J1
GND
J2
C1 .1uf
C2
.1uf
R1
100
JP1
U1
S3040
BYP
ASS
1k
R5
1k
R4
1k
R3
GND
dip4
U3
1k
R2
VEE
D1
1N4001
D2
C4
C3
1UF
C5
.1UF
L1
FB
L2
FB
VEE
CAP1
CAP2
C15
1uf
C16
.1uf
C17
100pf
C18
.1uf
C19
100pf
L4
FB
VCC
C20
1UF
C21
.1UF
C22
100PF
VEE
2 1
U2
PWRX2
C23
.1UF
C24
100PF
VCC
10UF
C25
VCC
VEE
J8
J7
CAP1
CAP2
C14
1uf
82
R7
82
R6
VEE
FILTER
BYPASS
J10
J9
VEE
VEE
GND
GND
FB
L3
C8
1UF
C9
.1UF
C10
100PF
C1
1
1UF
C12
.1UF
C13
100PF
D3
D(MELF)
1N4001
VEE
100PF
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
9
10
11
12
13
14
15
16
1
2
3
4
6
7
8
5
D(MELF)
3
4
6
5
1
2
8
7
nc
avcc
avee
avee
serdatiN
nc
refclkP
serdatiP
refclkN
lockrefN
sdn
vcc
vee
vcc
vee
lockdet
nc
serclkoP
serclkoN
avee
bypass
serdatoP
serdatoN
nc
nc
nc
avee
avcc
cap1
cap2
vee
vcc
Figure 3. EV3040 Evaluation Board Schematic
5
EV3040
OC-48 CLOCK RECOVERY UNIT EVALUATION BOARD
August 13, 1999
AMCC is a registered trademark of Applied Micro Circuits Corporation.
Copyright 1999 Applied Micro Circuits Corporation
AMCC reserves the right to make changes to its products or to discontinue any semiconductor product or service without notice, and
advises its customers to obtain the latest version of relevant information to verify, before placing orders, that the information being relied
on is current.
AMCC does not assume any liability arising out of the application or use of any product or circuit described herein, neither does it
convey any license under its patent rights nor the rights of others.
AMCC reserves the right to ship devices of higher grade in place of those of lower grade.
AMCC SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR
USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS.
Applied Micro Circuits Corporation 6290 Sequence Dr., San Diego, CA 92121
Phone: (858) 450-9333 (800) 755-2622 Fax: (858) 450-9885
http://www.amcc.com
C
E
R T I F I E
D
IS
O 9001
XX
XXXX
X
Prefix Device Package
X
I
F
E
R
P
E
C
I
V
E
D
E
G
A
K
C
A
P
d
r
a
o
B
n
o
i
t
a
u
l
a
v
E
V
E
0
4
0
3
P
F
Q
T
2
3
A
Ordering Information
PDF 
ZIP