AMCC
Production Release Information - The information con-
tained in this document is about a product in its fully tested
and characterized stage. All features described herein are
supported. Contact AMCC for updates to this document and
the latest product status.
Features
General Description
GANGES
STS-192 SONET/SDH FRAMER AND POS/ATM MAPPER
S19202 Block Diagram
PRODUCT BRIEF
Part Number - S19202CBI30
Product Brief Revision 3.1 - January 2002
Supports full duplex mapping of ATM cells or packets for a
single STS-192c/AU-4-64c, four STS-48c/AU-4-16c or six-
teen STS-12c/AU-4-4c SONET/SDH payloads.
Supports a single STS-192/STM-64 or quad STS-48/STM-
16 line interfaces on the line side and on the protection
port. Each STS-48/STM-16 can support a concatenated
payload or can be channelized down to STS-12c/AU-4-4c.
Terminates and generates SONET/SDH section, line, &
path layers on the line side and APS port, with transport/
section E1, E2, F1 and DCC overhead interfaces in both
transmit and receive directions.
Supports independent loop timing when in quad STS-48/
STM-16 mode.
Supports protection switching (APS) between two Ganges
devices or between two fiber optics modules
Provides an Optical Internetworking Forum (OIF) SFI-4
compliant 622.08 MHz, 16-bit bus LVDS interface on the
line side in both the TX and RX directions.
Provides a 64-bit, 200 MHz FlexBus 4 system interface
that supports the transfer of either packets or ATM cells.
Support mixed ATM and POS data termination, config-
urable on a per-tributary basis
16-bit synchronous microprocessor interface for configura-
tion, control, and status monitoring.
Packaged in a 624-pin CBGA.
Implemented in .18 micron, 1.8V and 2.5V technology.
The Ganges IC is a highly integrated VLSI device that pro-
vides full duplex mapping of Packets or ATM cells into
SONET/SDH payloads at rates up to 9.95Gb/s.
Ganges provides full section and line overhead processing
for either a single STS-192/STM-64, or four STS-48/STM-16.
It supports framing, scrambling and descrambling, alarm sig-
nal insertion and detection, and bit interleaved parity (B1/B2)
processing. It also provides path overhead processing for
STS-192c/AU-4-64c, STS-48c/AU-4-16c or STS-12c/AU-4-
4c SONET/SDH payloads and includes bit interleaved parity
(B3) processing.
The automatic protection switching (APS) port of the Ganges
supports generation and termination of SONET/SDH section
and line, as well as TOH insertion and extraction. This allows
inter-device protection switching between two Ganges
devices or intra-device protection between two fiber optics
modules.
The Ganges is SONET/SDH standards compliant with
Bellcore GR-253, ITU G.707, and ANSI T1.105 -1995.
Applications
Core ATM switches and IP Routers (POS)
ATM, POS and Frame Relay line cards in Edge and Metro
Switches
Direct Mapping of any traffic type in SONET/SDH STS-192/
STM-64 and STS-48/STM-16 payloads
L
I
NE SIDE
I
N
T
E
RF
ACE
RX_DATA_IN[15:0]
RX_CLK_IN_[1:4]
SRX_DATA_OUT[63:0]
FR
AM
LBK
SEL
TOH
MON.
STX_DATA_IN[63:0]
TX_DATA_OUT[15:0]
SPE/VC
GENERATOR
POH
MONITOR
POINTER
INTERPRETER
FRTX
LOC
DET
TX_CLK_OUT[1:4]
T
X
_T
OH
_
C
LK
_OU
T
[
1
:
4
]
T
X
_T
OH
_
F
R
M
_OU
T
[
1
:
4
]
T
X
_
T
O
H
_
D
A
T
A
_
IN
[
1
:4
]
/
HDLC /ATM
Proc
HDLC /ATM
Proc
Control
Control
SEL
D[1
5
:0
]
A
DDR
[
1
2
:
0
]
CS
N
WR
B(
R
W
B
)
RD
Y
B
(
D
T
A
CK
B
)
BU
SM
O
D
E
IN
T
B
MICROPROCESSOR I/F
RS
T
B
AP
S_
I
N
TB
PR
O
T
_
D
A
T
A_
O
U
T[
1
:
4
]
[
3
:
0
]
S
E
L
P
R
O
T
_
D
A
T
A
_
IN[1
:4
][
3
:
0
]
FRM x4
MUX
R
X
_T
OH
_
C
LK
_OU
T
I
1
:
4
]
R
X
_T
OH
_
F
R
M
_OU
T
1:
4]
R
X
_T
O
H
_D
A
T
A
_
OU
T
[
1
:
4]
TOH INSERT
FRMR
FRGEN
R
X
_L
OS
E
X
T
_[
1:
4]
SYSTEM
ATM/POS
FIFO
POH
GENERATION
P
R
O
T
_
C
L
K
_
I
N
[1
:4
]
P
R
OT
_C
L
K
_OU
T
[
1
:
4
]
x16
x16
x16
x16
x16
x16
x4
x4
x16
x16
INTRFC/
SYSTEM
ATM/POS
FIFO
INTRFC/
SYS
_
R
E
F
C
L
K_
I
N
SYS
_
A
SYN
C
_
FR
M
_
I
N
S
Y
S
_
R
E
F
C
LK
_O
U
T
RX
_
R
E
F
CL
K
_
I
N
[
1
:
4
]
R
X
_A
LM
_O
U
T
_
[
1:4
]
UP
CL
K
G
P
IO
[15
:
0]
TC
K
TD
O
TM
S
TD
I
TR
STB
TS
_
E
N
JTAG
RX PROT
PROT TX
FR GEN x4
R
X
_T
O
H
_D
A
T
A
_
OU
T
[
1
:
4]
PR
OT
_R
X_T
O
H
_
C
L
K_OU
T
I
1:
4]
PR
OT
_R
X_T
O
H
_
F
R
M
_
OU
T
1
:
4
]
RO
T
_
RX
_
T
O
H
_
D
A
T
A
_
O
U
T[
1
:
4
]
PR
O
T
_
T
X_
T
O
H
_
C
L
K_
O
U
T
[
1
:
4
]
PR
O
T
_
T
X_
T
O
H
_
F
R
M_
O
U
T
[
1
:
4
]
PR
O
T
_
T
X_
T
O
H
_
D
A
T
A
_
I
N
[
1
:
4
]
TOH EXTRACT
AMCC
200 Minuteman Road, Andover, MA 01810 Ph: (978) 247-8000 Fax: (978) 623-0024
STS-192 POS/ATM SONET/SDH MAPPER
Product Brief Revision 3.1 - January 2002
Ganges: S19202CBI30
PRODUCT BRIEF
Overview and Applications
SONET Processing
The S19202CBI30 supports either a single STS-192/
STM-64, or four STS-48/STM-16 SONET/SDH on its pri-
mary line interface as well as on its APS port. It provides
full duplex mapping of ATM cells or packets for STS-
192c/AU-4-64c, STS-48c/AU-4-16c, and/or STS-12c/
AU-4-4c SONET/SDH payloads.
A TOH/SOH interface provides direct add/drop capability
for E1, E2, F1, and both Section and Line DCC channels.
On the transmit side the S19202CBI30 generates sec-
tion, line, and path overhead. It performs framing pattern
insertion (A1, A2), scrambling, alarm signal insertion,
and generates section, line and path Bit Interleaved Par-
ity (B1/B2/B3) for far-end performance monitoring.
On the receive side the S19202CBI30 processes sec-
tion, line, and path overhead. It performs framing (A1,
A2), descrambling, alarm detection, pointer interpreta-
tion, bit interleaved parity monitoring (B1/B2/B3), and
error count accumulation for performance monitoring.
The APS interface is a mirror image of the primary line
interface that also operates either as a single STS-192/
or as four STS-48/STM-16 SONET/SDH Line. This
includes TOH add/drop as well section and line monitor-
ing. This APS port can directly interface to a fiber optics
module or to the APS port of a mate S19202CBI30.
ATM Processing
When configured for ATM cell processing, the
S19202CBI30's ATM processor(s) will perform all neces-
sary cell processing as defined by ATM UNI3.1 and ITU-
T I.432.1 and I.432.2.
HDLC Processing
When configured for POS mode, the S19202CBI30's
HDLC processor(s) provide the insertion of HDLC
framed packets into the STS SPE(s)/STM VC(s). The
S19202CBI30 performs HDLC processing as defined by
IETF RFCs 1661, 1662 and 2615. This includes optional
Address/Control field insertion and removal, Frame
Check Sequence (FCS) generation and check, transpar-
ency processing, HDLC frame delineation and optional
X43+1 scrambling and de-scrambling.
The HDLC processor(s) are also compatible with Frame
Relay Forum's FRF.14 specification.
Line-side Interface
On the main line-side and the APS port, the
S19202CBI30 supports a 16-bit parallel LVDS interface,
operating at 622MHz that is compliant with the OIF SFI-4
recommendation and designed to interface to AMCC's
S3091/92 and S3097/98 OC-192 physical layer devices.
For quad STS-48/STM-16 operation, the S19202CBI30
supports four 4-bit, 622 MHz, line interfaces and is
designed to interface to AMCC's S3455 OC-48 physical
layer device.
System Interface
The S19202CBI30 IC provides a 64-bit, 200MHz, Flex-
Bus 4
TM
system interface for the transport of either pack-
ets or ATM cells. The S19202CBI30 also includes a clear
channel mode that enables the direct mapping of system
payload from the system interface into Synchronous
Payload Envelope.
The FlexBus 4 interface complies with the OIF SPI-4
specification.
TX_DATA[15:0]
TX_SONETCLK
RX_SONETCLK_[1]
RX_DATA[15:0]
P/S
SONET XMIT
with
Clk Recovery
SerRxD
SerTxD
Microprocessor
Control
Control
Reference
Clock
Fiber Optic
Transceiver
SONET
Line Side
Interface
RX_LOS_[1]
S19202CBI30
GANGES
Addr
Data
12
TOH Insertion
and Extraction
TYPICAL APPLICATION: Ganges in a STS-192/AU-4-64 application with APS
OC-192
Line Interface
16
STX_DATA_IN[63:0]
AMCC S3091/92
&
S/P
SONET RCVR
SRX_DATA_OUT[63:0]
PROCESSOR
System Control SIgnals
Protection
Ganges
or
Fiber Optics
Module
APS
NETWORK
AMCC S3097/98
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