1
16 x 16 1.5 GBIT/S DIFFERENTIAL CROSSPOINT SWITCH
S2016
June 7, 1999 / Revision F
Figure 1. Functional Block Diagram
FEATURES
16 x 16 differential crosspoint switch
Full broadcast switching capability
Differential 10K PECL data path
Up to 1.5 Gbit/s NRZ data rate
TTL configuration controls
Reconfigurable without disturbing operation
120-pin PQFP/TEP package
+5V only power supply
APPLICATIONS
Internet switches
Digital video
Digital demultiplexing
Microwave or fiber-optic data distribution
High-speed automatic test equipment
Datacom or telecom switching
GENERAL DESCRIPTION
The S2016 is a very high-speed 16 x 16 differential
crosspoint switch with full broadcast capability. Any of its
16 differential PECL input signal pairs can be connected
to any or all of its 16 differential PECL output signal pairs.
The differential 10K PECL logic data path makes the
part ideal for high-speed applications. The differential
nature of the data path is retained throughout the
crosspoint structure, to minimize data distortion and to
handle NRZ data rates up to 1.5 gigabits per second.
TTL configuration controls simplify interfacing to slower
speed circuitry. Once a new configuration has been en-
tered into the configuration register file, the S2016 can be
completely reconfigured by pulsing the CONFIGN input.
16 x 16 1.5 GBIT/S DIFFERENTIAL CROSSPOINT SWITCH
S2016
PECL
Diff.
Input
Buffers
PECL
Diff.
Output
Buffers
16 x 16
Differential
Crosspoint
32
32
DIN00P
DIN15P
DOUT00P
DOUT15P
Active Configuration Latch
64
16 x 4
Configuration
Register File
64
IADDR0-3
DATA
16
4:16
Decode
EN
CONFIGN
LOADN
OADDR0-3
OADDR-
4
4
4
SELECT
DOUT00N
DOUT15N
DIN00N
DIN15N
DEVICE SPECIFICATION
2
16 x 16 1.5 GBIT/S DIFFERENTIAL CROSSPOINT SWITCH
S2016
June 7, 1999 / Revision F
DATA TRANSFER
For each configured connection between a differential
input pair and an enabled output pair, any data appear-
ing at the input pair will be passed immediately through
to the output pair.
RECONFIGURATION
The S2016 can be selectively reconfigured one output
pair at a time, or any number of output pairs can be
reconfigured simultaneously. Configuration data is
stored in 16 registers, one register for each output pair.
As shown in Figure 1, the configuration data is passed
in parallel from all 16 registers to a latch which holds the
active switch configuration. This two-stage arrange-
ment allows one or more output pairs to be reconfigured
simultaneously.
To connect an output pair to a given input pair, the
output pair to be reconfigured is selected using the
OADDR0-3 (OADDR3=MSB) inputs. With the output
pair configuration register selected, the desired input
pair selection is provided on the IADDR0-3
(IADDR3=MSB) inputs. The IADDR0-3 information will
be stored into the selected output pair configuration
register by the LOADN strobe.
When the differential switch is to be reconfigured, the
S2016 minimizes the time required through the use of
an active configuration latch. While the switch is opera-
tional, and prior to the time at which it must be
reconfigured, a new configuration can be loaded into
the output pair configuration registers. Once the 16
output pair configuration registers contain the desired
connection and output pair driver enable information,
the contents of the registers are transferred in parallel
to the active configuration latch by the CONFIGN strobe.
This allows multiple connections to be simultaneously
changed.
The configuration latch can be made transparent by
driving the CONFIGN input to a logic 0. When this is
done, changes strobed into the output pair configura-
tion registers by the LOADN input pair will be passed
immediately to the switch.
Figure 2. Data Transfer Waveforms
Figure 3. Reconfiguration Waveforms
tSUIA
LDMPW
tHIA
tSULC
CFMPW
tSUOA
tHOA
OADDR0-3
IADDR0-3
LOADN
VALID
VALID
CONFIGN
tCFDO
tLDDO
tDIDO
DIMPW
DINO-15 P/N
DOUTO-15 P/N
CONFIGN
LOADN
A
A
B
C
D
E
B
C
D
E
3
16 x 16 1.5 GBIT/S DIFFERENTIAL CROSSPOINT SWITCH
S2016
June 7, 1999 / Revision F
Table 1. Data Transfer Timing
1
Table 2. Reconfiguration Timing
2
Symbol
Description
Min.
Max.
Units
ps
ps
ps
ps
ps
ps
ps
1500
2000
500
1000
4200
4200
0
t
SUOA
t
HOA
t
SUIA
t
HIA
t
SULC
LD
MPW
CF
MPW
Setup time of OADDR0-3 before falling edge of LOADN
Hold time of OADDR0-3 after rising edge of LOADN
Pulse width low of LOADN
Pulse width low of CONFIGN
Setup time of IADDR0-3 before falling edge of LOADN
Hold time of IADDR0-3 after rising edge of LOADN
Setup time of LOADN to CONFIGN so that the falling edge
of CONFIGN will start reconfiguration
1. All timing measured from the V
CC
-1.3V point on the signals.
2. All timing measured from the 1.5V point on the signals.
Symbol
Description
Min.
Max.
Units
ns
ns
ns
ns
Mbit/s
0.650
3
6
7
1500
t
DIDO
t
CFDO
t
LDDO
DI
MPW
F
MAX
Propagation delay from DIN015 P/N to DOUT015 P/N
Propagation delay from falling edge of CONFIGN to
DOUT015 P/N valid
Propagation delay from falling edge of LOADN to
DOUT015 P/N valid (When CONFIGN is held low)
Pulse width of DIN015 P/N
Data rate
4
16 x 16 1.5 GBIT/S DIFFERENTIAL CROSSPOINT SWITCH
S2016
June 7, 1999 / Revision F
S2016 Pin Assignment and Descriptions
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16 x 16 1.5 GBIT/S DIFFERENTIAL CROSSPOINT SWITCH
S2016
June 7, 1999 / Revision F
S2016 Pin Assignment and Descriptions (Continued)
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