1
S2018
17 X 17 3.2 GBIT/S DIFFERENTIAL CROSSPOINT SWITCH
July 25, 2000 / Revision D
S2018
17 X 17 3.2 GBIT/S DIFFERENTIAL CROSSPOINT SWITCH
DEVICE
SPECIFICATION
FEATURES
SiGe BiCMOS Technology
17 x 17 differential crosspoint switch
Broadcast and multicast switching capability
Differential 200 mV to 1400 mV input data
Differential 200 mV to 1300 mV
programmable output swing
Up to 3.2 Gbps NRZ data rate
LVTTL configuration controls
Internal 100
line-to-line terminations on high-
speed differential inputs
Reconfigurable without disturbing operation
35 mm x 35 mm 352 pin SBGA package
+3.3 V only power supply
4 W typical power dissipation with
800 mV output swing
Complies with Bellcore and ITU-T Standard
APPLICATIONS
Dense Wavelength Division Multiplexing
(DWDM) systems
Internet switches
Digital video
Digital demultiplexing
Microwave or fiber-optic data distribution
High-speed automatic test equipment
Datacom or telecom switching
GENERAL DESCRIPTION
The S2018 is a high speed 17 x 17 differential cross-
point switch with full broadcast capability. Any of its
17 differential LVPECL input signal pairs can be con-
nected to any or all of its 17 differential CML output
signal pairs.
The differential 10K LVPECL logic data path makes
the part ideal for high-speed applications. The differ-
ential nature of the data path is retained throughout
the crosspoint structure to minimize data distortion
and to handle NRZ data rates up to 3.2 gigabits per
second. The high-speed serial inputs to the S2018
are internally biased and have internal 100
line-to-
line terminations.
LVTTL configuration controls simplify interfacing to
slower speed circuitry. Once a new configuration has
been entered into the configuration register file, the
S2018 can be completely reconfigured by pulsing
the CONFIGN input.
Figure 1 shows a system block diagram incorporat-
ing the S2018 with AMCC serial backplane devices.
Figure 2 shows the basic operation of the switch.
Figure 1. System Block Diagram
.
.
.
.
.
.
.
.
16
0
S2062
S2004
.
.
.
.
.
.
.
.
0
16
S2064
S2002
S2018
Crosspoint
Switch
Crosspoint
Control
(
P &
DRAM)
2
S2018
17 X 17 3.2 GBIT/S DIFFERENTIAL CROSSPOINT SWITCH
July 25, 2000 / Revision D
Figure 2. Functional Block Diagram
Diff.
LVPECL
Input
Buffers
Diff.
CML
Output
Buffers
17 x 17
Differential
Crosspoint
34
34
DIN0P
DIN16P
DOUT0P
DOUT16P
Active Configuration Latch
85
17 x 5
Configuration
Register File
85
IADDR[4:0]
DATA
17
5:17
Decode
EN
CONFIGN
LOADN
CSN
OADDR[4:0]
5
5
SELECT
DOUT0N
DOUT16N
DIN0N
DIN16N
VADJUST3
VADJUST2
VADJUST1
VCSHIGH
F
F
I
D
T
U
P
N
I
4
R
D
D
A
I
3
R
D
D
A
I
2
R
D
D
A
I
1
R
D
D
A
I
0
R
D
D
A
I
F
F
I
D
T
U
P
T
U
O
4
R
D
D
A
O
3
R
D
D
A
O
2
R
D
D
A
O
1
R
D
D
A
O
0
R
D
D
A
O
0
N
I
D
1
N
I
D
2
N
I
D
3
N
I
D
4
N
I
D
5
N
I
D
6
N
I
D
7
N
I
D
8
N
I
D
9
N
I
D
0
1
N
I
D
1
1
N
I
D
2
1
N
I
D
3
1
N
I
D
4
1
N
I
D
5
1
N
I
D
6
1
N
I
D
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
X
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
X
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
X
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
X
0
T
U
O
D
1
T
U
O
D
2
T
U
O
D
3
T
U
O
D
4
T
U
O
D
5
T
U
O
D
6
T
U
O
D
7
T
U
O
D
8
T
U
O
D
9
T
U
O
D
0
1
T
U
O
D
1
1
T
U
O
D
2
1
T
U
O
D
3
1
T
U
O
D
4
1
T
U
O
D
5
1
T
U
O
D
6
1
T
U
O
D
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
X
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
X
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
X
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
X
Table 1. Input/Output Address of S2018
Note: X denotes don't care
3
S2018
17 X 17 3.2 GBIT/S DIFFERENTIAL CROSSPOINT SWITCH
July 25, 2000 / Revision D
DATA TRANSFER
For each configured connection between a differen-
tial input pair and an enabled output pair, any data
appearing at the input pair will be passed immedi-
ately through to the output pair.
CONFIGURATION
The S2018 can be selectively configured one output
pair at a time, or any number of output pairs simulta-
neously. Configuration data is stored in 17 registers,
one register for each output pair. The data in these
17 configurations register makes up the configura-
tion register file. As shown in Figure 2, the configura-
tion data is passed in parallel from all 17 registers to
a latch, which holds the active switch configuration.
This two-stage arrangement allows one or more out-
put pairs to be configured simultaneously. A Chip
Select pin (CSN) is provided to simplify interfacing
this switch to the system microprocessor.
The S2018 minimizes the configuration time through
the use of the active configuration latch. While the
switch is operational, and prior to the time at which it
must be reconfigured, a new configuration is loaded
into the configuration register file. Once the configu-
ration register file contains the desired connection
information, the contents of the registers are trans-
ferred in parallel to the active configuration latch by
the CONFIGN strobe.
To connect an output to a given input, the output to
be configured is selected using the OADDR[4:0]
(OADDR4=MSB) inputs. See Table 1. With the out-
put configuration register selected, the desired input
selection must be provided in the IADDR[4:0]
(IADDR4=MSB) inputs. The IADDR[4:0] information
is stored into the selected output configuration regis-
ter by the LOADN strobe. The configuration process
is described by the flow chart in Figure 5.
The active configuration latch can be made transpar-
ent by activating the CONFIGN input. When this is
done, changes strobed into the output pair configu-
ration registers by the LOADN input pair will be
passed immediately to the switch.
The S2018 supports both broadcast and multicast
operation: any of the 17 differential input pairs can
be connected to any or all of the 17 differential out-
put pairs.
OUTPUT SWING ADJUST
The S2018 output swing can be adjusted by con-
necting one or more of the VADJUSTx pins to the
VCSHIGH pin according to Table 2. Note that as the
output swing is increased, the power dissipated by
the part is proportionally increased (See Table 10).
Figure 3. Data Transfer Waveforms
Figure 4. Reconfiguration Waveforms
1
t
s
u
j
d
a
V
2
t
s
u
j
d
a
V
3
t
s
u
j
d
a
V
)
.
f
f
i
D
p
p
V
m
(
x
x
T
U
O
D
T
O
T
O
T
O
T
O
T
T
O
O
T
T
O
O
O
T
T
T
T
0
4
2
0
4
4
0
0
6
0
8
7
0
4
9
0
0
1
1
0
6
2
1
Table 2. Output Swing Adjust Pin Settings
Note: T = Ties pin(s) VADJUSTx to pin VCSHIGH
O = Open
tCFDO
tLDDO
tDIDO
DIMPW
DIN[16:0]P/N
DOUT[16:0]P/N
CONFIGN
CSN
LOADN
A
A
B
C
D
E
B
C
D
E
tCSDO
tSUIA
LDMPW
tHIA
tSULC
CFMPW
tSUOA
tHOA
OADDR[4:0]
IADDR[4:0]
CSN
LOADN
VALID
VALID
CONFIGN
tSUCS
tHCS
4
S2018
17 X 17 3.2 GBIT/S DIFFERENTIAL CROSSPOINT SWITCH
July 25, 2000 / Revision D
Activate
CSN
Configure OADDR[4:0]
to desired output.
See Table 1.
Configure IADDR[4:0]
to desired input.
See Table 1.
Strobe LOADN
to store the input address (IADDR[4:0])
in the section of the Configuration
Register File pointed to by the
output register (OADDR[4:0])
Configure
another
output?
Strobe CONFIGN
to store all connections to the
Active Configuration Latch
YES
NO
Figure 5. S2018 Configuration Flow Chart
5
S2018
17 X 17 3.2 GBIT/S DIFFERENTIAL CROSSPOINT SWITCH
July 25, 2000 / Revision D
Table 3. Data Transfer Timing
1,2
r
e
t
e
m
a
r
a
P
n
o
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p
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D
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p
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x
a
M
s
t
i
n
U
s
n
o
i
t
i
d
n
o
C
t
O
D
I
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N
/
P
]
0
:
6
1
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N
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f
y
a
l
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p
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/
P
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5
.
1
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1
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4
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0
:
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1
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2
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1
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P
6
1
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(
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.
e
n
il
-
o
t
-
e
n
il
1. All data transfer timing measured from the crossing point of the differential inputs to the crossing point of the differential outputs.
2. All data measured with 800 mVpp swing.
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