1
GIGABIT ETHERNET CHIPSET
S2046/S2047
May 16, 2000 / Revision NC
BiCMOS PECL CLOCK GENERATOR
FEATURES
Functionally compliant with the IEEE 802.3z
Specification
S2046 transmitter incorporates phase-locked
loop (PLL) providing clock synthesis from low-
speed reference
S2047 receiver PLL configured for clock and
data recovery
1250 Mb/s (Gigabit Ethernet) operation
10-bit or 20-bit parallel TTL compatible
interface
1 watt typical power dissipation for chipset
+3.3/+5 V power supply
Low-jitter serial PECL compatible interface
Lock detect
Local loopback
Compact 52 pin PQFP package
Fibre Channel framing performed by receiver
Continuous downstream clocking from receiver
TTL compatible outputs possible with +5V I/O
power supply
APPLICATIONS
High-speed data communications
Ethernet backbone connections
Mainframe
Workstation
Frame buffer
Switched networks
Data broadcast environments
Proprietary extended backplanes
GENERAL DESCRIPTION
The S2046 and S2047 transmitter and receiver pair
are designed to perform high-speed serial data trans-
mission over fiber optic or coaxial cable interfaces
conforming to the requirements of the IEEE 802.3z
specification. The chipset is Gigabit Ethernet compli-
ant and supports 1250 Mb/s with an associated 10 or
20-bit data word.
The chipset performs parallel-to-serial and serial-to-
parallel conversion and framing for block-encoded
data. The S2046 on-chip PLL synthesizes the high-
speed clock from a low-speed reference. The S2047
on-chip PLL synchronizes directly to incoming digital
signals, to receive the data stream. The transmitter
and receiver each support differential PECL-compat-
ible I/O for fiber optic component interfaces, to
minimize crosstalk and maximize data integrity. Local
loopback allows for system diagnostics. The I/O sec-
tion can operate from either a +3.3 V or a +5 V power
supply. With a 3.3 V power supply the chipset dissi-
pates only 1 W typically.
Figure 1 shows a typical network configuration incor-
porating the chipset.
Figure 1. System Block Diagram
DEVICE SPECIFICATION
S2046/S2047
GIGABIT ETHERNET CHIPSET
Optical
TX
Optical
RX
Optical
RX
Optical
TX
S2047
RX
S2046
TX
S2046
TX
S2047
RX
Gigabit
Ethernet
Controller
Gigabit
Ethernet
Controller
2
GIGABIT ETHERNET CHIPSET
S2046/S2047
May 16, 2000 / Revision NC
Loopback
Local loopback is supported by the chipset, and pro-
vides a capability for performing offline testing of the
interface to ensure the integrity of the serial channel
before enabling the transmission medium. It also al-
lows for system diagnostics.
S2046/S2047 OVERVIEW
The S2046 transmitter and S2047 receiver provide
serialization and deserialization functions for block-
encoded data to implement a Gigabit interface.
Operation of the S2046/S2047 chips is straightfor-
ward, as depicted in Figure 2. The sequence of
operations is as follows:
Transmitter
1. 10/20-bit parallel input
2. Parallel-to-serial conversion
3. Serial output
Receiver
1. Clock and data recovery from serial input
2. Serial-to-parallel conversion
3. Frame detection
4. 10/20-bit parallel output
The 10/20-bit parallel data handled by the S2046 and
S2047 devices should be from a DC-balanced en-
coding scheme, such as the 8B/10B transmission
code, in which information to be transmitted is en-
coded 8 bits at a time into 10-bit transmission
characters.
Internal clocking and control functions are transpar-
ent to the user. Details of data timing can be seen in
Figure 5.
A lock detect feature is provided on the receiver, which
indicates that the PLL is locked (synchronized) to the
data stream.
Figure 2. Interface Diagram
Parallel
Data In
S2046
Transmitter
S2047
Receiver
REFCLK
Lock
Detect
REFCLK
RCLK
Parallel
Data Out
RCLKN
Loopback
Loopback
SYNC
Serial
Data
TCLK
S2046 TRANSMITTER
Architecture/Functional Description
The S2046 transmitter accepts parallel input data and
serializes it for transmission over fiber optic or coaxial
cable media. The S2046 is fully compliant with the
IEEE 802.3z Specification, and supports the Gigabit
Ethernet data rate of 1250 Mbit/sec.
The parallel input data word can be either 10 bits or
20 bits wide, depending upon DWS pin selection. A
block diagram showing the basic chip function is
shown in Figure 3.
CONTROL
LOGIC
TEST
D[0:19]
OE1
OE0
DWS
REFSEL
REFCLK
2:1
10
10
20
10
PLL CLOCK
MULTIPLIER
F0 = F1 X 10/20
SHIFT
REGISTER
TX
TY
TLX
TLY
TCLK
TCLKN
DIVIDE-BY-2
D
Q
Figure 3. S2046 Functional Block Diagram
3
GIGABIT ETHERNET CHIPSET
S2046/S2047
May 16, 2000 / Revision NC
Parallel/Serial Conversion
The parallel-to-serial converter takes in 10-bit or
20-bit wide data from the input latch and converts it
to a serial data stream. Parallel data is latched into
the transmitter on the positive going edge of REFCLK.
The data is then clocked synchronous to the clock
synthesis unit serial clock into the serial output shift
register. The shift register is clocked by the internally
generated bit clock which is 10 or 20 times the
REFCLK input frequency. The state of the serial out-
puts is controlled by the output enable pins, OE0 and
OE1. D[10] is transmitted first in 10-bit mode. D[0] is
transmitted first in 20-bit mode. Table 2 shows the
mapping of the parallel data to the 8B/10B codes.
10-Bit/20-Bit Mode
The S2046 operates with either 10-bit or 20-bit paral-
lel data inputs. Word width is selectable via the DWS
pin. In 10-bit mode, D[10:19] are used and D[0:9] are
ignored.
Reference Clock Input
The reference clock input (REFCLK) must be sup-
plied with a PECL single-ended AC coupled crystal
clock source with 100 PPM tolerance to assure that
the transmitted data meets the Fibre Channel
and IEEE 802.3z Specification frequency limits. The
internal serial clock is frequency locked to the
reference clock. Refer to Table 1 for reference clock
frequencies.
Table 1. Transmitter Operating Modes
Data Rate
(Mbps)
REFSEL
DWS
Word
Width
(Bits)
Reference
Clock
Frequency
(MHz)
1250.0
1250.0
20
10
0
1
TCLK/TCLKN
Frequency
(MHz)
62.50
62.5
62.50
125.0
0
1
First Data Byte
Second Data Byte
19
18
17
16
15
14
13
12
11
10
j
h
g
f
i
e
d
c
b
a
9
8
7
6
5
4
3
2
1
0
TX[0:19] or
RX[0:19]
8B/10B alphabetic
representation
j
h
g
f
i
e
d
c
b
a
First bit transmitted in 20-bit mode
First bit transmitted in 10-bit mode
Table 2. Data Mapping to 8B/10B Alphabetic Representation
Figure 4. S2047 Functional Block Diagram
PLL CLOCK
RECOVERY
2:1
D
20
D
BITCLK
Q
SYNC
DETECT
LOGIC
CONTROL
LOGIC
RX
REFSEL
REFCLK
LOCK_REF
RY
RLX
RLY
LPEN
DWS
SYNCEN
LOCKDETN
D[0:19]
RCLK
SYNC
RCLKN
SHIFT
REGISTER
DIVIDER
4
GIGABIT ETHERNET CHIPSET
S2046/S2047
May 16, 2000 / Revision NC
Figure 6. Interface Diagram
Data In
S2046 Fibre
Channel
Transmitter
S2047
Fibre
Channel
Receiver
CLK
Data Out
Local
Loopback
S2047
Fibre
Channel
Receiver
S2046
Fibre
Channel
Transmitter
Local
Loopback
OE0, OE1
CLK
Data Out
Data In
OE0, OE1
S2047 RECEIVER
Architecture/Functional Description
The S2047 receiver is designed to implement the
IEEE 802.3z Specification receiver functions. A block
diagram showing the basic chip function is provided
in Figure 4.
Whenever a signal is present, the S2047 attempts to
achieve synchronization on both bit and transmission-
word boundaries of the received encoded bit stream.
Received data from the incoming bit stream is pro-
vided on the device's parallel data outputs.
The S2047 accepts serial encoded data from a fiber
optic or coaxial cable interface. The serial input stream
is the result of the serialization of 8B/10B encoded
data by a compatible transmitter. Clock recovery is
performed on-chip, with the output data presented to
the transmission layer as 10-bit or 20-bit parallel data.
The chip operates at the Gigabit Ethernet frequency
of 1250 Mbit/s.
Serial/Parallel Conversion
Serial data is received on the RX, RY pins. The PLL
clock recovery circuit will lock to the data stream if
the clock to be recovered is within
100 PPM of the
internally generated bit rate clock. The recovered clock
is used to retime the input data stream. The data is
then clocked into the serial to parallel output regis-
ters. The parallel data out can be either 10 or 20 bits
wide determined by the state of the DWS pin. The
word clock (RCLKN) is synchronized to the incoming
data stream word boundary by the detection of the
K28.5 synchronization pattern (0011111010, positive
running disparity).
10-Bit/20-Bit Mode
The S2047 will operate with either 10-bit or 20-bit
parallel data outputs. This option is selectable via
the DWS pin. See Table 3. In 10-bit mode, the 10-bit
data word is output on both D[10:19] and D[0:9]
simultaneously.
1. A.X. Widmer and P.A. Franaszek, "A Byte-Oriented DC Balanced (0,4) 8B/10B Transmission Code," IBM Research Report RC 9391,
May 1982.
REFCLK
(Input)
RCLK
(Output)
SYNC
(Output)
PARALLEL
DATA BUS
(Input)
K28.5,
Byte 1
of Data
Byte 2, 3
of Data
Byte 4, 5
of Data
Byte 6, 7
of Data
Byte 8, 9
of Data
Byte 10,
11 of Data
Byte 12,
13 of Data
Byte 14,15
of Data
K28.5
Byte 16
of Data
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
PARALLEL
DATA BUS
(Output)
SERIAL DATA
S
2
0
4
6
S
2
0
4
7
K28.5
K28.5,
Byte 1
of Data
Byte 2, 3
of Data
Byte 4, 5
of Data
Byte 6, 7
of Data
Byte 8, 9
of Data
Byte 10,
11 of Data
Byte 12,
13 of Data
Byte 14,15
of Data
K28.5 D16
Figure 5. Functional Waveform
5
GIGABIT ETHERNET CHIPSET
S2046/S2047
May 16, 2000 / Revision NC
Reference Clock Input
The reference clock input must be supplied with a PECL
single-ended AC coupled crystal clock source at
100 PPM
tolerance. See Table 3 for reference clock frequencies.
Framing
The S2047 provides SYNC character recognition and
data word alignment of the TTL level compatible out-
put data bus. During the data realignment process,
the RCLKN phase will be adjusted. No glitches will
occur in the RCLKN signal due to the realignment. In
systems where the SYNC detect function is undes-
ired, a LOW on the SYNCEN input disables the SYNC
function and the data will be "un-framed."
When framing is disabled by low SYNCEN, the S2047
simply achieves bit synchronization and begins to de-
liver parallel output data words whenever it has
received full transmission words. No attempt is made
to synchronize on any particular incoming character.
The SYNC output signal will go high whenever a K28.5
character (positive disparity) is present on the parallel
data outputs. The SYNC output signal will be low at
all other times. This is true whether the S2047 is
operating in 10-bit mode or in 20-bit mode.
Data Rate
(Mbps)
REFSEL
DWS
Word
Width
(Bits)
Reference
Clock
Frequency
(MHz)
1250.0
1250.0
20
10
0
1
RCLK/RCLKN
Frequency
(MHz)
62.50
62.5
62.50
125.0
0
1
Table 3. Receiver Operating Modes
Lock Detect
The S2047 lock detect function indicates the state of
the phase-locked loop (PLL) clock recovery unit. The
PLL will indicate lock after the start of receiving serial
data inputs. If the serial data inputs have an instanta-
neous phase jump (from a serial switch, for example)
the PLL will not indicate an out-of-lock state, but will
recover the correct phase alignment within 250 bit
times. If a run length of 64 bits is exceeded, or if the
transition density is less than 12%, the loop will be
declared out of lock and will attempt to re-acquire bit
synchronization. When lock is lost, the PLL will shift
from the serial input data to the reference clock, so
that correct frequency downstream clocking will be
maintained.
In any transfer of PLL control from the serial data to
the reference clock, the RCLK/RCLKN output remains
phase continuous and glitch free, assuring the integ-
rity of downstream clocking.
Start-Up Procedure
The clock recovery PLL requires an initilization pro-
cedure to correctly achieve lock on the serial data
inputs. At power-up or loss of lock, the PLL must first
acquire frequency lock to the local reference clock.
This can be accomplished connecting the LOCK_REF
pin to a 10 ms reset signal. If this is not possible, the
PLL can also be initialized by guaranteeing that no
data is seen at the serial data inputs for a minimum
of 10 ms upon power-up. If the serial data inputs
cannot be controlled, then the S2047 can be put into
the loopback mode and the loopback outputs of the
S2046 must be quiescent for a minimum of 10 ms
after power-up.
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