1
GIGABIT ETHERNET CHIPSET
S2046/S2050
March 29, 2000 / Revision B
BiCMOS PECL CLOCK GENERATOR
Figure 1. System Block Diagram
DEVICE
SPECIFICATION
S2046/S2050
GIGABIT ETHERNET CHIPSET
Optical
TX
Optical
RX
Optical
RX
Optical
TX
S2050
RX
S2046
TX
S2046
TX
S2050
RX
Gigabit
Ethernet
Controller
Gigabit
Ethernet
Controller
FEATURES
Functionally compliant with the 802.3z specification
S2046 transmitter incorporates phase-locked
loop (PLL) providing clock synthesis from low-
speed reference
S2050 receiver PLL configured for clock and
data recovery
1250 Mbps (Gigabit Ethernet) operation
10- or 20-bit parallel TTL compatible interface
+3.3/+5V power supply
Low-jitter serial PECL compatible interface
Lock detect
Local loopback
Compact 52 PQFP package
Gigabit Ethernet framing performed by receiver
Continuous downstream clocking from receiver
TTL compatible outputs possible with +5V I/O
power supply
APPLICATIONS
High-speed data communications
Ethernet backbone connections
Mainframe
Workstation
Frame buffer
Switched networks
Data broadcast environments
Proprietary extended backplanes
GENERAL DESCRIPTION
The S2046 and S2050 transmitter and receiver pair
are designed to perform high-speed serial data trans-
mission over fiber optic or coaxial cable interfaces
conforming to the requirements of the proposed 802.3z
specification. The chipset is Gigabit Ethernet compli-
ant and supports 1250 Mbps with an associated 10
or 20-bit data word.
The chipset performs parallel-to-serial and serial-to-
parallel conversion and framing for block-encoded
data. The S2046 on-chip PLL synthesizes the high-
speed clock from a low-speed reference. The S2050
on-chip PLL synchronizes directly to incoming digital
signals, to receive the data stream. The transmitter
and receiver each support differential PECL-compat-
ible I/O for fiber optic component interfaces, to
minimize crosstalk and maximize data integrity. Local
loopback allows for system diagnostics. The I/O sec-
tion can operate from either a +3.3V or a +5V power
supply. (See
Ordering Information.)
Figure 1 shows a typical network configuration incor-
porating the chipset.
2
GIGABIT ETHERNET CHIPSET
S2046/S2050
March 29, 2000 / Revision B
Figure 2. Interface Diagram
Parallel
Data In
S2046
Transmitter
S2050
Receiver
REFCLK
LOCKDETN
REFCLK
RCLK
Parallel
Data Out
RCLKN
Loopback
Loopback
SYNC
Serial
Data
TCLK
TCLKN
TLX/Y
TX/Y
RX/Y
RLX/Y
CONTROL
LOGIC
TEST
D[19:0]
OE1
OE0
DWS
REFSEL
REFCLK
2:1
10
10
20
10
PLL CLOCK
MULTIPLIER
F0 = F1 X 10/20
SHIFT
REGISTER
TX
TY
TLX
TLY
TCLK
TCLKN
DIVIDE-BY-2
D
Q
Figure 3. S2046 Functional Block Diagram
S2046/S2050 OVERVIEW
The S2046 transmitter and S2050 receiver provide
serialization and deserialization functions for block-
encoded data to implement a Gigabit interface.
Operation of the S2046/S2050 chips is straightfor-
ward, as depicted in Figure 2. The sequence of
operations is as follows:
Transmitter
1. 10/20-bit parallel input
2. Parallel-to-serial conversion
3. Serial output
Receiver
1. Clock and data recovery from serial input
2. Serial-to-parallel conversion
3. Frame detection
4. 10/20-bit parallel output
The 10/20-bit parallel data handled by the S2046 and
S2050 devices should be from a DC-balanced en-
coding scheme, such as the 8B/10B transmission
code, in which information to be transmitted is en-
coded 8 bits at a time into 10-bit transmission
characters.
Internal clocking and control functions are transpar-
ent to the user. Details of data timing can be seen in
Figure 5.
A lock detect feature is provided on the receiver,
which indicates that the PLL is locked (synchronized)
to the data stream.
Loopback
Local loopback is supported by the chipset, and pro-
vides a capability for performing offline testing of the
interface to ensure the integrity of the serial channel
before enabling the transmission medium. It also al-
lows for system diagnostics.
S2046 TRANSMITTER
Architecture/Functional Description
The S2046 transmitter accepts parallel input data and
serializes it for transmission over fiber optic or coaxial
cable media. The S2046 is fully compliant with the
proposed 802.3z Specification, and supports the Gi-
gabit Ethernet data rate of 1250 Mbps.
3
GIGABIT ETHERNET CHIPSET
S2046/S2050
March 29, 2000 / Revision B
Table 1. Transmitter Operating Modes
Data Rate
(Mbps/sec)
REFSEL
DWS
Word
Width
(Bits)
Reference
Clock
Frequency
(MHz)
1250.0
1250.0
20
10
0
1
TCLK/TCLKN
Frequency
(MHz)
62.5
62.5
62.5
125.0
0
1
Table 2. Data Mapping to 8B/10B Alphabetic Representation
Figure 4. S2050 Functional Block Diagram
PLL CLOCK
RECOVERY
2:1
D
20
D
BITCLK
Q
SYNC
DETECT
LOGIC
CONTROL
LOGIC
RX
REFSEL
REFCLK
LOCKREFN
RY
RLX
RLY
LPEN
DWS
SYNCEN
LOCKDETN
D(0:19)
RCLK
SYNC
RCLKN
SHIFT
REGISTER
DIVIDER
The parallel input data word can be either 10 bits or
20 bits wide, depending upon DWS pin selection. A
block diagram showing the basic chip function is
shown in Figure 3.
Parallel/Serial Conversion
The parallel-to-serial converter takes in 10-bit or 20-
bit wide data from the input latch and converts it to a
serial data stream. Parallel data is latched into the
transmitter on the positive going edge of REFCLK.
The data is then clocked synchronous to the clock
synthesis unit serial clock into the serial output shift
register. The shift register is clocked by the internally
generated bit clock which is 10 or 20 times the
REFCLK input frequency. The state of the serial out-
puts is controlled by the output enable pins, OE0 and
OE1. D[10] is transmitted first in 10-bit mode. D[0] is
transmitted first in 20-bit mode. Table 2 shows the
mapping of the parallel data to the 8B/10B codes.
10-Bit/20-Bit Mode
The S2046 operates with either 10-bit or 20-bit paral-
lel data inputs. Word width is selectable via the DWS
pin. In 10-bit mode, D[10-19] are used and D[0-9] are
ignored. See Table 2.
Reference Clock Input
The reference clock input (REFCLK) must be supplied
with a PECL single-ended AC coupled crystal clock
source with 100 PPM tolerance to assure that the trans-
mitted data meets the proposed 802.3z Specification
frequency limits. The internal serial clock is frequency
locked to the reference clock. Refer to Table 1 for
reference clock frequencies.
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First bit transmitted in 20-bit mode
4
GIGABIT ETHERNET CHIPSET
S2046/S2050
March 29, 2000 / Revision B
1. A.X. Widmer and P.A. Franaszek, "A Byte-Oriented DC Balanced (0,4) 8B/10B Transmission Code," IBM Research Report RC 9391,
May 1982.
REFCLK
(Input)
RCLK
(Output)
SYNC
(Output)
PARALLEL
DATA BUS
(Input)
K28.5,
Byte 1
of Data
Byte 2, 3
of Data
Byte 4, 5
of Data
Byte 6, 7
of Data
Byte 8, 9
of Data
Byte 10,
11 of Data
Byte 12,
13 of Data
Byte 14,15
of Data
K28.5
Byte 16
of Data
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
PARALLEL
DATA BUS
(Output)
SERIAL DATA
S
2
0
4
6
S
2
0
5
0
K28.5
K28.5,
Byte 1
of Data
Byte 2, 3
of Data
Byte 4, 5
of Data
Byte 6, 7
of Data
Byte 8, 9
of Data
Byte 10,
11 of Data
Byte 12,
13 of Data
Byte 14,15
of Data
K28.5 D16
Figure 5. Functional Waveform
S2050 RECEIVER
Architecture/Functional Description
The S2050 receiver is designed to implement the
802.3z specification receiver functions. A block dia-
gram showing the basic chip function is provided in
Figure 4.
Whenever a signal is present, the S2050 attempts to
achieve synchronization on both bit and transmission-
word boundaries of the received encoded bit stream.
Received data from the incoming bit stream is pro-
vided on the device's parallel data outputs.
The S2050 accepts serial encoded data from a fiber
optic or coaxial cable interface. The serial input stream
is the result of the serialization of 8B/10B encoded
data by a compatible transmitter. Clock recovery is
performed on-chip, with the output data presented to
the transmission layer as 10- or 20-bit parallel data.
The chip operates at the Gigabit Ethernet frequency
of 1250 Mbps.
Serial/Parallel Conversion
Serial data is received on the RX, RY pins. The PLL
clock recovery circuit will lock to the data stream if
the clock to be recovered is within
100 PPM of the
internally generated bit rate clock. The recovered clock
is used to retime the input data stream. The data is
then clocked into the serial to parallel output regis-
ters. The parallel data out can be either 10 or 20 bits
wide determined by the state of the DWS pin. The
word clock (RCLKN) is synchronized to the incoming
data stream word boundary by the detection of the
COMMA synchronization pattern (0011111XXX, positive
running disparity).
10-Bit/20-Bit Mode
The S2050 will operate with either 10-bit or 20-bit par-
allel data outputs. This option is selectable via the
DWS pin. See Tables 2 and 3. In 10-bit mode, the
10:bit data word is output on D[10:19], and D[0:9] are
driven to the logic high state.
5
GIGABIT ETHERNET CHIPSET
S2046/S2050
March 29, 2000 / Revision B
Figure 6. Interface Diagram
Data In
S2046
Gigabit
Ethernet
Transmitter
S2050
Gigabit
Ethernet
Receiver
RCLK
Data Out
Local
Loopback
S2050
Gigabit
Ethernet
Receiver
S2046
Gigabit
Ethernet
Transmitter
Local
Loopback
TX/Y
TLX/Y
RX/Y
RLX/Y
TLX/Y
RX/Y
TX/Y
RLX/Y
OE1
OE0
LPEN
RCLK
Data Out
LPEN
Data In
OE0, OE1
Data Rate
(Mbits/sec)
REFSEL
DWS
Word
Width
(Bits)
Reference
Clock
Frequency
(MHz)
1250.0
1250.0
20
10
0
1
RCLK/RCLKN
Frequency
(MHz)
62.50
62.5
62.50
125.0
0
1
Table 3. Receiver Operating Modes
Table 4. Response of PLL Loop Circuit to Input Data Rate Variation
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Reference Clock Input
The reference clock input must be supplied with a PECL
single-ended AC coupled crystal clock source at
100 PPM
tolerance. See Table 3 for reference clock frequencies.
Framing
The S2050 provides SYNC character recognition and
data word alignment of the TTL level compatible out-
put data bus. During the data realignment process,
the RCLKN phase will be adjusted, and the byte pre-
vious to the comma character will be lost. No glitches
will occur in the RCLKN signal due to the realign-
ment. In systems where the SYNC detect function is
undesired, a LOW on the SYNCEN input disables the
SYNC function and the data will be "unframed".
When framing is disabled by low SYNCEN, the S2050
simply achieves bit synchronization and begins to de-
liver parallel output data words whenever it has
received full transmission words. No attempt is made
to synchronize on any particular incoming character.
The SYNC output signal will go high whenever a
COMMA character (0011111XXX, positive running dis-
parity) is present on the parallel data outputs. The
SYNC output signal will be low at all other times. This
is true whether the S2050 is operating in 10-bit mode
or in 20-bit mode.
Lock Detect
The S2050 lock detect function indicates the state of
the phase-locked loop (PLL) clock recovery unit. The
PLL will indicate lock within 2.5
s after the start of
receiving serial data inputs. If the serial data inputs
have an instantaneous phase jump (from a serial
switch, for example) the PLL will not indicate an out-
of-lock state, but will recover the correct phase
alignment. If a run length of 80-160 bits is exceeded
the loop will declare loss of lock. Input data rate varia-
tion (compared to REFCLK) can also cause loss of
lock. Table 4 shows the response of the PLL loop
circuit to input data rate variation. When lock is lost,
the PLL will attempt to reacquire bit synchronization,
and will shift from the serial input data to the refer-
ence clock so that the correct frequency downstream
clocking will be maintained.
6
GIGABIT ETHERNET CHIPSET
S2046/S2050
March 29, 2000 / Revision B
The LOCKDETN output will go to inactive when no
data is present on the serial data inputs. When
LOCKDETN is in the inactive state, it indicates that
the PLL is locking to the local reference clock to main-
tain downstream clocking. When LOCKDETN is in
the active state, it indicates that the PLL is attempting
to lock to the incoming serial data. When serial data
is restored, the LOCKDETN output will stay in the
active state.
When lock is lost, the PLL will attempt to reacquire bit
synchronization, and will shift from the serial input
data to the reference clock so that the correct down-
stream clocking will be maintained. The PLL will
continuously shift between the reference clock and
the input data until input data has been restored. While
the PLL is locked to the reference clock, LOCKDETN
will remain active, with one exception: when all of the
following conditions are met, the LOCKDETN output
toggle between active and inactive, reflecting the in-
ternal PLL shift between reference clock and input
data: (a) LOCKREFN is not active; (b) the signal (or
noise) on the high-speed input is above the voltage
input sensitivity threshold; (c) the signal (or noise) on
the high-speed input varies from the reference clock
by more than 244 ppm, and (d) the signal (or noise)
on the high-speed input passes the run length crite-
ria. When these conditions are met, LOCKDETN will
toggle, and the RCLK/RCLKN outputs will also shift
slightly in frequency.
In any transfer of PLL control from the serial data to
the reference clock, the RCLK/RCLKN output remains
phase continuous and glitch free, assuring the integ-
rity of downstream clocking.
OTHER OPERATING MODES
Loopback
The S2046 and S2050 have secondary high-speed I/O
to provide a local loopback path. The local loopback
configuration is shown in Figure 6. When OE1 is ac-
tive on the S2046, the high-speed data is passed out
the TLX/Y output. Operation of the TLX/Y output is
independent of the TX/Y output--data can be simul-
taneously output on both. With LPEN active on the
S2050, data on the RLX/Y input is passed through to
the parallel output. The local loopback path provides
the capability to perform off-line testing and system
diagnostics.
Operating Frequency Range
The S2046 and S2050 are optimized for operation at
the Gigabit Ethernet rate of 1250.0 Mbit/s. REFCLK
must be selected to be within 100 ppm of the desired
byte or word clock rate.
Test Modes
The TEST pin on the S2046 and the SYNCEN pin on
the S2050 provide a PLL bypass mode that can be
used for operating the digital area of the chip. In this
mode, clock signals are input through the reference
clock pins. This can be used for testing the device
during the manufacturing process or during an off-line
self-test. Sync detection is always enabled in test mode.
The SYNCEN input on the S2050 must transition
through mid-state in less than five REFCLK periods
to insure that PLL bypass mode is not exerted. In
order to guarantee that the S2050 enters PLL bypass
mode, SYNCEN must be held in mid state for more
than seven REFCLK cycles.
7
GIGABIT ETHERNET CHIPSET
S2046/S2050
March 29, 2000 / Revision B
Table 5. S2046 Pin Assignment and Descriptions
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8
GIGABIT ETHERNET CHIPSET
S2046/S2050
March 29, 2000 / Revision B
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Table 5. S2046 Pin Assignment and Descriptions (Continued)
9
GIGABIT ETHERNET CHIPSET
S2046/S2050
March 29, 2000 / Revision B
Table 6. S2050 Pin Assignment and Descriptions
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10
GIGABIT ETHERNET CHIPSET
S2046/S2050
March 29, 2000 / Revision B
Table 6. S2050 Pin Assignment and Descriptions (Continued)
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11
GIGABIT ETHERNET CHIPSET
S2046/S2050
March 29, 2000 / Revision B
Figure 7. S2046 and S2050 52 PQFP Pinouts
TTLVCC
=
+5 V or +3.3 V for S2046 and S2050A; +3.3 V for S2050A-3
AVCC
=
+3.3 V
ECLVCC
=
+3.3 V
ECLIOVCC =
+3.3 V
ECLIOVEE =
0V
TTLGND
=
0V
ECLVEE
=
0V
AVEE
=
0V
1
2
3
4
5
6
7
8
9
10
11
16
17
18
19
20
21
22
23
24
25
26
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
S2050
28
27
ECLVCC
D15
D14
TTLVCC
D13
D12
TTLGND
D11
D10
REFSEL
D9
D8
ECLVCC
14
15
TTLGND
D2
D3
TTLVCC
TTLGND
D4
D5
TTLVCC
D6
D7
ECLVEE
D0
D1
52
51
LOCKREFN
RCLK
RCLKN
ECLVEE
TTLGND
D19
TTLVCC
D18
D17
TTLGND
D16
LOCKDETN
SYNC
12
13
ECLVEE
REFCLK
SYNCEN
DWS
AVEE
AVEE
AVCC
LPEN
RX
RY
RLX
RLY
ECLVCC
1
2
3
4
5
6
7
8
9
10
11
16
17
18
19
20
21
22
23
24
25
26
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49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
S2046
28
27
ECLVCC
D11
D10
D9
D8
TTLGND
AVEE
AVCC
D7
D6
D5
D4
AVCC
14
15
REFCLK
TTLVCC
REFSEL
DWS
GND
ECLVCC
D0
D1
D2
D3
AVEE
TTLGND
TTLGND
52
51
D19
D18
D17
D16
NC
NC
D15
D14
D13
D12
ECLVEE
ECLVEE
ECLVEE
12
13
OE1
OE0
ECLIOVCC
TLY
TLX
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ECLIOVEE
TX
TY
ECLIOVCC
TCLKN
TCLK
ECLVEE
TOP VIEW
TOP VIEW
12
GIGABIT ETHERNET CHIPSET
S2046/S2050
March 29, 2000 / Revision B
Figure 8. 52 PQFP-HS -- (10mm x 10mm) Plastic Quad Flat Pack
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Table 7. Thermal Management
13
GIGABIT ETHERNET CHIPSET
S2046/S2050
March 29, 2000 / Revision B
Table 8. Absolute Maximum Ratings
The following are the absolute maximum device stress ratings. Stresses beyond those listed may cause
permanent damage to the device. These are stress ratings only. Operation of the device at these or any other
conditions beyond those indicated in the electrical characteristics section of this document is not implied.
Table 9. Recommended Operating Conditions
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Electrostatic Discharge (ESD) Ratings.
The S2046 and S2050 are rated to the following ESD voltages based on the human body model. All
pins are rated above 500 V.
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14
GIGABIT ETHERNET CHIPSET
S2046/S2050
March 29, 2000 / Revision B
Table 10. S2046 DC Characteristics
Table 11. S2050 DC Characteristics
Parameters
Description
Min
Typ
Units
Conditions
VOH
Output HIGH Voltage (TTL)
3.3V Power Supply
3.3V Power Supply
5V Power Supply
2.1
2.2
2.7
2.0
0
--
-500
Max
--
--
--
--
V
V
V
VCC = min, IOH = -2.4mA
VCC = min, IOH = -.1mA
VCC = min, IOH = -1mA
ICC
Supply Current
255
280
mA
Outputs open, VCC = VCC max
PD
Power Dissipation
3.3V Supply
5V Supply
0.91
1.1
1.0
1.2
W
W
Outputs open, VCC = VCC max
Outputs open, VCC = VCC max
VOL
Output LOW Voltage (TTL)
3.3V Power Supply
5V Power Supply
.5
.5
V
V
VCC = min, IOL = 2.4mA
VCC = min, IOL = 4mA
VIH
VIL
IIH
IIL
Input HIGH Voltage (TTL)
Input LOW Voltage (TTL)
Input HIGH Current (TTL)
Input LOW Current (TTL)
--
0.8
50
-50
V
V
A
A
--
VIN = 2.4V
VIN = 0.5V
440
100
1300
--
VINCLK
VDIFF
Single-ended REFCLK input swing
1300
mV
mV
AC coupled
Min. differential input voltage
swing for differential PECL
inputs
Parameters
Description
Min
Typ
Units
Conditions
VOH
Output HIGH Voltage (TTL)
3.3V Power Supply
3.3V Power Supply
5V Power Supply
2.1
2.2
2.7
2.0
0
--
-500
Max
--
--
--
--
V
V
V
VCC = min, IOH = -2.4mA
VCC = min, IOH = -.1mA
VCC = min, IOH = -1mA
ICC
Supply Current
123
160
mA
Outputs open, VCC = VCC max
PD
Power Dissipation
.406
.554
W
Outputs open, VCC = VCC max
VOL
Output LOW Voltage (TTL)
3.3V Power Supply
5V Power Supply
.5
.5
V
V
VCC = min, IOL = 2.4mA
VCC = min, IOL = 4mA
VIH
VIL
IIH
IIL
Input HIGH Voltage (TTL)
Input LOW Voltage (TTL)
Input HIGH Current (TTL)
Input LOW Current (TTL)
0.8
50
-50
V
V
A
A
--
--
VIN = 2.4V
VIN = 0.5V
440
600
--
--
VINCLK
VOUT
Single-ended REFCLK input swing
Serial Output Voltage Swing
1300
1300
mV
mV
AC coupled
50
to VCC -2.0V
15
GIGABIT ETHERNET CHIPSET
S2046/S2050
March 29, 2000 / Revision B
Table 12. Reference Clock Requirements
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Table 13. Transmitter Timing
1.
All AC measurements are made from the reference voltage level of the clock (1.4V) to the valid input or output data levels
(.8V or 2.0V).
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16
GIGABIT ETHERNET CHIPSET
S2046/S2050
March 29, 2000 / Revision B
Table 13. Receiver Timing
Note:
All AC measurements are made from the reference voltage level of the clock (1.4V) to the valid input or output data
levels (.8V or 2.0V).
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17
GIGABIT ETHERNET CHIPSET
S2046/S2050
March 29, 2000 / Revision B
Figure 11. Transmitter Timing Diagram (10-bit Mode)
D0
2
4
6
8
D10
12
14
16
18
1
3
5
7
D9
11
13
15
17
D19
T1
T2
SERIAL
DATA OUT
REFCLK
D[10:19] 10 BIT DATA
Figure 13. Receiver Timing Diagram (10-bit Mode)
D0
2
4
6
8
D10
12
14
16
18
T5
1
3
5
7
D9
11
13
15
17
D19
T7
T6
T6
K28.5
DATA
T7
REFCLK (125 MHz)
SERIAL DATA IN
RCLK (62.5 MHz)
RCLKN (62.5 MHz)
and SYNC
D[10:19]
Figure 12. Receiver Timing Diagram (20-bit Mode)
D0
2
4
6
8
10
12
14
16
18
1
3
5
7
9
11
13
15
17
D19
T4
T3
SERIAL
DATA OUT
REFCLK
D[0:19]
Figure 14. Receiver Timing Diagram (20-bit Mode)
D0
2
4
6
8
10
12
14
16
18
T8
T9
1
3
5
7
9
11
13
15
17
D19
SERIAL
DATA IN
REFCLK
RCLKN
D[0:19] and SYNC
18
GIGABIT ETHERNET CHIPSET
S2046/S2050
March 29, 2000 / Revision B
Tr
Tf
80%
50%
20%
80%
50%
20%
Backplane
150
150
0.01
F
0.01
F
0.01
F
0.01
F
V
CC
- 0.65 V
100
Tr
Tf
90%
50%
10%
90%
50%
10%
Amplitude
Bit Time
24
%
.10
0
-0.2
0.2
0.3
0.5
0.7
0.8
1.0
1.3
0
.30 .40
.60 .70
.90 1.0
Normalized Time
Normalized Amplitude
Figure 15. Serial Input Rise and Fall Time
Figure 16. Serial Output Load
Figure 17. High Speed Differential Inputs
Figure 18. TTL Input Rise and Fall Time
Figure 19. Receiver Input Eye Diagram Jitter Mask
Figure 20. Acquisition Time Eye Diagram
19
GIGABIT ETHERNET CHIPSET
S2046/S2050
March 29, 2000 / Revision B
Ordering Information
Example:
S2046B-5--S2046 in a 52 PQFP package shipped in trays.
AMCC is a registered trademark of Applied Micro Circuits Corporation.
Copyright 2000 Applied Micro Circuits Corporation
AMCC reserves the right to make changes to its products or to discontinue any semiconductor product or service without notice, and
advises its customers to obtain the latest version of relevant information to verify, before placing orders, that the information being relied
on is current.
AMCC does not assume any liability arising out of the application or use of any product or circuit described herein, neither does it
convey any license under its patent rights nor the rights of others.
AMCC reserves the right to ship devices of higher grade in place of those of lower grade.
AMCC SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR
USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS.
Applied Micro Circuits Corporation 6290 Sequence Dr., San Diego, CA 92121
Phone: (858) 450-9333 (800)755-2622 Fax: (858) 450-9885
http://www.amcc.com
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Grade Part No. Package Configuration
X
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