1
HIGH PERFORMANCE SERIAL INTERFACE CIRCUITS
S2042/S2048
April 10, 2000 / Revision B
Optical
TX
Optical
RX
Optical
RX
Optical
TX
S2048
RX
S2042
TX
S2042
TX
S2048
RX
Fibre
Channel
Controller
Fibre
Channel
Controller
BiCMOS PECL CLOCK GENERATOR
DEVICE
SPECIFICATION
HIGH PERFORMANCE SERIAL INTERFACE CIRCUITS
S2042/S2048
FEATURES
Functionally compliant with ANSI X3T11 Fibre
Channel physical and transmission protocol
standards
S2042 transmitter incorporates phase-locked loop
(PLL) providing clock synthesis from low-speed
reference
S2048 receiver PLL configured for clock and
data recovery
1062.5, 531.25 and 265.625 Mbps operation
10- or 20-bit parallel TTL compatible interface
+3.3 V/+5 V power supply
Low-jitter serial PECL compatible interface
Lock detect
Local loopback
10mm x 10mm 52 PQFP package
Fibre Channel framing performed by receiver
Continuous downstream clocking from receiver
TTL compatible outputs
APPLICATIONS
High-speed data communications
Supercomputer/Mainframe
Workstation
Switched networks
Proprietary extended backplanes
Mass storage devices/RAID drives
GENERAL DESCRIPTION
The S2042 and S2048 transmitter and receiver pair
are designed to perform high-speed serial data trans-
mission over fiber optic or coaxial cable interfaces
conforming to the requirements of the ANSI X3T11
Fibre Channel specification. The chipset is select-
able to 1062.5, 531.25 or 265.625 Mbps data rates
with associated 10- or 20-bit data word.
The chipset performs parallel-to-serial and serial-to-
parallel conversion and framing for block-encoded
data. The S2042 on-chip PLL synthesizes the high-
speed clock from a low-speed reference. The S2048
on-chip PLL synchronizes directly to incoming digital
signals to receive the data stream. The transmitter
and receiver each support differential PECL-compat-
ible I/O for fiber optic component interfaces, to
minimize crosstalk and maximize data integrity. Lo-
cal loopback allows for system diagnostics.
Figure 1 shows a typical network configuration incor-
porating the chipset.
Figure 1. System Block Diagram
2
HIGH PERFORMANCE SERIAL INTERFACE CIRCUITS
S2042/S2048
April 10, 2000 / Revision B
Loopback
Local loopback is supported by the chipset, and pro-
vides a capability for performing offline testing of the
interface to ensure the integrity of the serial channel
before enabling the transmission medium. It also al-
lows for system diagnostics.
OVERVIEW
The S2042 transmitter and S2048 receiver provide
serialization and deserialization functions for block-
encoded data to implement a Fibre Channel interface.
Operation of the S2042/S2048 chips is straightfor-
ward, as depicted in Figure 2. The sequence of
operations is as follows:
Transmitter
1. 10/20-bit parallel input
2. Parallel-to-serial conversion
3. Serial output
Receiver
1. Clock and data recovery from serial input
2. Serial-to-parallel conversion
3. Frame detection
4. 10/20-bit parallel output
The 10/20-bit parallel data handled by the S2042 and
S2048 devices should be from a DC-balanced encod-
ing scheme, such as the 8B/10B transmission code,
in which information to be transmitted is encoded 8
bits at a time into 10-bit transmission characters.
Internal clocking and control functions are transparent to
the user. Details of data timing can be seen in Figure 5.
A lock detect feature is provided on the receiver,
which indicates that the PLL is locked (synchronized)
to the reference clock or the data stream.
S2042 TRANSMITTER FUNCTIONAL
DESCRIPTION
The S2042 transmitter accepts parallel input data
and serializes it for transmission over fiber optic or
coaxial cable media. The chip is fully compatible with
the ANSI X3T11 Fibre Channel standard, and sup-
ports the Fibre Channel standard's data rates of
1062.5, 531.25 and 265.625 Mbps.
The parallel input data word can be either 10 bits or
20 bits wide, depending upon DWS pin selection. A
block diagram showing the basic chip operation is
shown in Figure 3.
Figure 3. S2042 Functional Block Diagram
CONTROL
LOGIC
TEST
D[0:19]
OE1
OE0
DWS
REFCLK
REFSEL
RATESEL
2:1
10
10
20
10
DIVIDE-BY-2
PLL CLOCK
MULTIPLIER
F0 = F1 X 10/20
SHIFT
REGISTER
TX
TY
TLX
TLY
TCLK
TCLKN
DIVIDE-BY-2
D
Q
Figure 2. Fibre Channel Interface Diagram
Parallel
Data In
S2042
Transmitter
S2048
Receiver
REFCLK
LOCKDETN
REFCLK
RCLK
Parallel
Data Out
Loopback
Loopback
SYNC
Serial
Data
TCLK
TLX/Y
TX/Y
RLX/Y
RX/Y
3
HIGH PERFORMANCE SERIAL INTERFACE CIRCUITS
S2042/S2048
April 10, 2000 / Revision B
Reference Clock Input
The reference clock input (REFCLK) must be sup-
plied with a single-ended AC coupled crystal clock
source with
100 PPM tolerance to assure that the
transmitted data meets the Fibre Channel frequency
limits. The internal serial clock is frequency locked to
the reference clock. The word rate clock (TCLK, TCLKN)
output frequency is determined by the selected oper-
ating speed and word width. Refer to Table 1 for
TCLK/TCLKN clock frequencies.
Table 1. Transmitter Operating Modes
Data Rate
(Mbits/sec)
RATESEL
REFSEL
DWS
Word
Width
(Bits)
Reference
Clock
Frequency
(MHz)
1062.5
1062.5
531.25
531.25
265.625
0
0
1
1
Open
10
20
10
20
10
1
0
1
0
1
TCLK/TCLKN
Frequency
(MHz)
53.125
53.125
53.125
26.5625
26.5625
106.25
53.125
53.125
26.5625
26.5625
1
0
1
0
1
Parallel/Serial Conversion
The parallel-to-serial converter takes in 10-bit or 20-
bit wide data from the input latch and converts it to a
serial data stream. Parallel data is latched into the
transmitter on the positive going edge of REFCLK.
The data is then clocked synchronous to the clock
synthesis unit serial clock into the serial output shift
register. The shift register is clocked by the internally
generated bit clock which is 10 times the REFCLK
input frequency. The state of the serial outputs is
controlled by the output enable pins, OE0 and OE1.
D[10] is transmitted first in 10-bit mode. D[0] is trans-
mitted first in 20-bit mode. Table 2 shows the mapping
of the parallel data to the 8B/10B codes.
10-Bit/20-Bit Mode
The S2042 operates with either 10-bit or 20-bit par-
allel data inputs. Word width is selectable via the
DWS pin. In 10-bit mode, D[10:19] are used and
D[0:9] are ignored. (See Table 2).
First Data Byte
Second Data Byte
19
18
17
16
15
14
13
12
11
10
j
h
g
f
i
e
d
c
b
a
9
8
7
6
5
4
3
2
1
0
TX[0:19] or
RX[0:19]
8B/10B alphabetic
representation
j
h
g
f
i
e
d
c
b
a
First bit transmitted in 20-bit mode
First bit transmitted in 10-bit mode
Table 2. Data Mapping to 8B/10B Alphabetic Representation
Figure 4. S2048 Functional Block Diagram
PLL CLOCK
RECOVERY
2:1
D
20
D
BITCLK
Q
SYNC
DETECT
LOGIC
CONTROL
LOGIC
RX
REFCLK
REFSEL
RATESEL
LOCKREFN
RY
RLX
RLY
LPEN
DWS
SYNCEN
LOCKDETN
D[0:19]
RCLK
SYNC
RCLKN
SHIFT
REGISTER
4
HIGH PERFORMANCE SERIAL INTERFACE CIRCUITS
S2042/S2048
April 10, 2000 / Revision B
S2048 RECEIVER FUNCTIONAL
DESCRIPTION
The S2048 receiver is designed to implement the
ANSI X3T11 Fibre Channel specification receiver
functions. A block diagram showing the basic chip
function is provided in Figure 4.
Whenever a signal is present, the S2048 attempts to
achieve synchronization on both bit and transmis-
sion-word boundaries of the received encoded bit
stream. Received data from the incoming bit stream
is provided on the device's parallel data outputs.
The S2048 accepts serial encoded data from a fiber
optic or coaxial cable interface. The serial input stream
is the result of the serialization of 8B/10B encoded
data by an FC compatible transmitter. Clock recov-
ery is performed on-chip, with the output data
presented to the Fibre Channel transmission layer as
10- or 20-bit parallel data. The chip is programmable
to operate at the Fibre Channel specified operating
frequencies of 1062.5, 531.25 and 265.625 Mbps.
Serial/Parallel Conversion
Serial data is received on the RX and RY pins. The
PLL clock recovery circuit will lock to the data stream
if the clock to be recovered is within
100 PPM of the
internally generated bit rate clock. The recovered clock
is used to retime the input data stream. The data is
then clocked into the serial-to-parallel output regis-
ters. The parallel data out can be either 10- or 20-bits
wide determined by the state of the DWS pin. The
word clock (RCLK) is synchronized to the incoming
data stream word boundary by the detection of the
Fiber Channel COMMA synchronization pattern
(0011111XXX, positive running disparity).
10-Bit/20-Bit Mode
The S2048 will operate with either 10-bit or 20-bit
parallel data outputs. This option is selectable via
the DWS pin. See Tables 1 and 3. In 10-bit mode,
D[10:19] are used and D[0:9] are driven to the logic
high state.
Reference Clock Input
The reference clock input must be supplied with a single-
ended AC coupled crystal clock source at
100 PPM
tolerance. See Table 3 for reference clock frequencies.
Framing
The S2048 provides SYNC character recognition and
data word alignment of the TTL level compatible out-
put data bus. During the data realignment process
the RCLK phase will be adjusted. No glitches will
occur in the RCLK signal due to the realignment. In
systems where the SYNC detect function is undes-
ired, a LOW on the SYNCEN input disables the SYNC
function and the data will be "un-framed".
When framing is disabled by low SYNCEN, the S2048
achieves bit synchronization and begins to deliver
parallel output data words whenever it has received
full transmission words. No attempt is made to syn-
chronize on any particular incoming character.
REFCLK
(Input)
RCLK
(Output)
SYNC
(Output)
PARALLEL
DATA BUS
(Input)
K28.5,
Byte 1
of Data
Byte 2, 3
of Data
Byte 4, 5
of Data
Byte 6, 7
of Data
Byte 8, 9
of Data
Byte 10,
11 of Data
Byte 12,
13 of Data
Byte 14,15
of Data
K28.5
Byte 16
of Data
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
PARALLEL
DATA BUS
(Output)
SERIAL DATA
S
2
0
4
2
S
2
0
4
8
K28.5
K28.5,
Byte 1
of Data
Byte 2, 3
of Data
Byte 4, 5
of Data
Byte 6, 7
of Data
Byte 8, 9
of Data
Byte 10,
11 of Data
Byte 12,
13 of Data
Byte 14,15
of Data
K28.5 D16
Figure 5. Functional Waveform
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HIGH PERFORMANCE SERIAL INTERFACE CIRCUITS
S2042/S2048
April 10, 2000 / Revision B
The SYNC output signal will go high whenever a
COMMA character (0011111XXX, positive running
disparity) is present on the parallel data outputs. The
SYNC output signal will be low at all other times.
This is true whether the S2048 is operating in 10-bit
mode or in 20-bit mode.
Lock Detect
The S2048 lock detect function indicates the state of
the phase-locked loop (PLL) clock recovery unit. The
PLL will indicate lock within 2.5
s after the start of
receiving serial data inputs. If a run length of 80-160
bits is exceeded, the loop will declare loss of lock.
Input data rate variation (compared to REF_CLK) can
also cause loss of lock. Table 4 shows the response
of the PLL loop circuit to input data rate variation.
When lock is lost, the PLL will attempt to re-aquire
bit synchronization, and will shift from the serial input
data to the reference clock so that the correct fre-
quency downstream clocking will be maintained.
Table 3 . Receiver Operating Modes
Data Rate
(Mbits/sec)
RATESEL
REFSEL
DWS
Word
Width
(Bits)
Reference
Clock
Frequency
(MHz)
1062.5
1062.5
531.25
531.25
265.625
0
0
1
1
Open
10
20
10
20
10
1
0
1
0
1
RCLK/RCLKN
Frequency
(MHz)
53.125
53.125
53.125
26.5625
26.5625
106.25
53.125
53.125
26.5625
26.5625
1
0
1
0
1
The LOCKDETN output will go inactive when no data
is present on the serial data input. When LOCKDETN
is in the inactive state, it indicates that the PLL is
locking to the local reference clock to maintain down-
stream clocking. When LOCKDETN is in the active
state, it indicates that the PLL is attempting to lock to
the in coming serial data. When serial data is restored,
the LOCKDETN output will stay in the active state.
When lock is lost, the PLL will attemp to reaquire bit
synchronization, and will shift from the serial input data
to the reference clock so that the correct downstream
clocking will be maintained. The PLL will continuously
shift between the reference clock and the input data
until input data has been restored. While the PLL is
locked to the reference clock, LOCKDETN will remain
active, with one exception. When all of the following
conditions are met the LOCKDETN output will toggle
between active and inactive, reflecting the internal PLL
shift between reference clock and input data: (a)
LOCKREFN is not active, (b) the signal (or noise) on
the high-speed input is above the voltage input sensitiv-
ity threshold, (c) the signal (or noise) on the high-speed
input varies from the reference clock by more than 244
ppm, and (d) the signal (or noise) on the high-speed
input passes the run length criteria. When these condi-
tions are met, LOCKDETN will toggle and the RCLK/
RCLKN outputs will also shift slightly in frequency.
Table 4. Response of PLL Loop Circuit to Input Data Rate Variation
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Figure 6. Loopback Interface Diagram
Data In
S2042
Fibre
Channel
Transmitter
S2048
Fibre
Channel
Receiver
RCLK
Data Out
Local
Loopback
S2048
Fibre
Channel
Receiver
S2042
Fibre
Channel
Transmitter
Local
Loopback
OE0
OE1
LPEN
TX/Y
RX/Y
TLX/Y
RLX/Y
TX/Y
RX/Y
TLX/Y
RLX/Y
RCLK
Data Out
Data In
OE1
OE0
LPEN
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