1
S2058
PORT BYPASS AND REPEATER FOR FIBRE CHANNEL ARBITRATED LOOP
S2058
FEATURES
ANSI X3T11 Fibre Channel Compatible
Monolithic Clock Recovery Unit
Re-times & Buffers Received Data
Jitter Peaking < 0.15 dB
Lock Detect Function
Run Length Violation Detector
Frequency Detection
Port Bypass Circuit
Suitable for both Coaxial and Optical Link
APPLICATIONS
Low Power Operation 0.425W, Typical
106.25 or 53.125 MHz Reference Clock
28-Pin SOIC Package
3.3V Supply
GENERAL DESCRIPTION
The Fibre Channel Port Bypass with Repeater Cir-
cuit is used in full-speed (1.0625 Gb/s) Disk Arrays.
The S2058 block diagram is shown in Figure 1. It
contains a monolithic Clock Recovery Unit (CRU), a
lock detect feature and a port bypass Circuit. The
CRU may be used alone to implement a general
purpose Repeater needed for many Disk Array and
Switch applications where a re-timed and buffered
signal is required. The S2058 may be used to imple-
ment a single chip Arbitrated Loop Port Bypass Re-
timing Node. The S2058 performs the function of a
port bypass circuit followed by a clock and data
retiming Phase Locked Loop (CDR). The CDR re-
times incoming serial data, detects whether a valid
signal is present and outputs a low jitter serial data
stream.
FUNCTIONAL DESCRIPTION
The S2058 performs two functions. The first is a Port
Bypass Circuit (PBC) for nodes in a FC-AL system.
The low jitter accumulation of the Port Bypass Path
is essential in these systems. The second function is
to retime and restore signal quality in RAID drives
using the FC-AL link configuration. The low jitter
transfer peaking and the high jitter tolerance specifi-
cations of the Clock and Data Recovery PLL are
essential in these applications. In addition, the Lock
Figure 1. S2058 Block Diagram
PORT BYPASS AND REPEATER FOR FIBRE CHANNEL ARBITRATED LOOP
detect circuit monitors the incoming signals for valid
8B/10B run length, transition density and frequency.
The output of this circuit is useful for link perfor-
mance monitoring and detection of channel present.
Jitter Performance
The S2058 complies with the minimum jitter toler-
ance requirements proposed by the Fibre Channel
jitter working group when used with differential in-
puts and outputs as shown in Figure 2. In addition,
the S2058 is designed for minimum jitter generation
and jitter transfer specifications. This allows the opti-
mum system design for arbitrated loop architectures.
Jitter Tolerance
Input jitter tolerance is defined as the amplitude of
frequency dependent, random and deterministic jitter
that causes the clock recovery PLL to violate the
BER specifications. Input jitter tolerance specifica-
tions are shown in Figures 3 and 4.
CDR
normal
0
1
S2058
LCKREFN
REFCLK
LOCKDET
SEL
DDI P/N
DDO P/N
IN P/N
OUT P/N
LPF1
LPF2
REFSEL
TEST
24
2.2
F (X7R Type)
24
DEVICE
SPECIFICATION
3
S2058
PORT BYPASS AND REPEATER FOR FIBRE CHANNEL ARBITRATED LOOP
FREQUENCY DEPENDENT JITTER
TOLERANCE
Frequency Dependent Input jitter tolerance is de-
fined as the peak to peak amplitude of sinusoidal
jitter applied on the input signal. See Figure 3.
Random Jitter Tolerance
Random Jitter Tolerance is the amount of jitter with a
gaussian distribution that the clock recovery PLL
must tolerate.
Deterministic Jitter Tolerance
Deterministic Jitter Tolerance is the amount of Deter-
ministic jitter that the clock recovery PLL must toler-
ate.
JITTER TRANSFER
Jitter transfer is defined as the ratio of jitter on the
output signal to the jitter applied on the input signal
versus frequency. Jitter transfer requirements are
shown in Figure 5. The measurement condition is
that input sinusoidal jitter up to the mask level in
Figure 4 is applied and the output jitter is measured
for compliance to the mask of Figure 5. The jitter
transfer mask includes specifications for both jitter
peaking and bandwidth.
LOCK DETECT
The S2058 lock detect circuit monitors the selected
input signal to detect the presence of the channel.
This is done by monitoring the run length, transition
density and frequency content of the incoming data.
The frequency monitor circuit checks the difference
between the divided down recovered clock and the
externally supplied reference clock (REFCLK). If the
frequency difference of the recovered clock and the
reference clock varies by more than +/- 240 ppm the
part will be declared out of lock. In the out of lock
state the PLL will lock to the local reference clock
and periodically poll the serial data input looking for
data with valid frequency content. In this state the
LOCKDET output will shift between high and low
states, mirroring the PLL as it locks to REFCLK
(LOCKDET INACTIVE) and input data (LOCKDET
ACTIVE).
Figure 3. Input Jitter Tolerance
Figure 5. Jitter Transfer Specification
Figure 4. Frequency Dependent Jitter
Tolerance Mask
FREQ DJ/ISI
RJ
10
-12
0
329
612
940
PS
BER
Jitter
Transfer
Acceptable Range
slope = -20 dB/decade
fc = 1.25 MHz
Peaking = 0.15 dB
f
c
/25,000
(42.5 KHz)
Cut-off Freq A
f
c
/1,667
(637 KHz)
Cut-off Freq B
TIME (Unit Interval - UI)
1.5
Frequency (Hz)
(KHz) = Cut-off Freq @ 1,0625 Gbps
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