S2078

DUAL FIBRE CHANNEL TRANSCEIVER

June 20, 2000 / Revision B

S2078

DUAL FIBRE CHANNEL TRANSCEIVER

DEVICE
SPECIFICATION

FEATURES

· Functionally compliant with ANSI X3T11 Fibre

Channel physical and transmission protocol
standards

· 1062 MHz (Fibre Channel) operating rate

- Half rate operation

· Dual Transmitter incorporating phase-locked

loop (PLL) clock synthesis from low speed
reference

· Dual Receiver PLL provides clock and data

recovery

· Internally Series terminated TTL outputs

· Low-jitter serial PECL interface

· Local Loopback

· Interfaces with coax, twinax, or fiber optics

· Single +3.3V supply, 1.33 W power dissipation

· Compact 21mm x 21mm 156 TBGA package

APPLICATIONS

High-speed data communications

· Switched networks

· Data broadcast environments

· Fibre Channel Switches

GENERAL DESCRIPTION

The S2078 dual transmitter and receiver chip is de-
signed to provide two channels of high-speed serial
data transmission over fiber optic or copper interfaces
conforming to the requirements of the ANSI X3T11
Fibre Channel specification. The chip runs at 1062.5
Mbps serial data rate with an associated 10-bit paral-
lel data word. The chip provides two separate receive
PLLs which can be operated asyncronously.

Each bi-directional channel provides parallel-to-se-
rial and serial-to-parallel conversion, clock genera-
tion and recovery, and framing. The on-chip transmit
PLL synthesizes the high-speed clock from a low-
speed reference. The on-chip dual receive PLL is
used for clock recovery and data re-timing on the
two independent data inputs. The transmitter and re-
ceiver each support differential PECL-compatible I/O
for copper or fiber optic component interfaces and
provide excellent signal integrity. Local loopback
mode allows for system diagnostics. The chip re-
quires a 3.3V power supply and dissipates 1.33
watts.

Figure 1 shows the use of the S2062 and S2078 in a
Fibre Channel application. Figure 2 summarizes the
input/output signals of the device. Figures 3 and 4
show the transmit and receive block diagrams, re-
spectively.

Figure 1. Typical Dual Fibre Channel Application

MAC

(ASIC)

S2062

DUAL

FIBRE

CHANNEL

INTERFACE

MAC

(ASIC)

TO SERIAL
BACKPLANE

S2078

FC INTERFACE

SERIAL BP DRIVER

S2078

DUAL FIBRE CHANNEL TRANSCEIVER

June 20, 2000 / Revision B

TRANSMITTER DESCRIPTION

The transmitter section of the S2078 contains a
single PLL which is used to generate the serial rate
transmit clock for all transmitters. Transmitter
functionalities shown schematically in Figure 3. Two
channels are provided with a variety of options re-
garding input clocking and loopback. The transmit-
ters operate at 1.062 GHz, 10 or 20 times the
reference clock frequency.

Data Input

The S2078 has been designed to simplify the paral-
lel interface data transfer and provides flexibility in
the clocking of parallel data. Prior implementations
of this function have either forced the user to syn-
chronize transmit data to the reference clock or to
provide the output clock as a reference to the PLL,
resulting in increased jitter at the serial interface.
The S2078 incorporates a unique FIFO structure
which enables the user to provide a "clean" refer-
ence source for the PLL and to accept a separate
external clock which is used exclusively to reliably
clock data into the device.

The S2078 also provides a system clock output,
TCLKO, which is derived from the internal VCO. The
frequency of this output is constant at the parallel
word rate, 1/10 the serial data rate, regardless of
whether the reference is provided at 1/10 or 1/20 the
serial data rate. This clock can be used by upstream
circuitry as a system clock. See Table 1.

Data to be input to the S2078 should be coded to
insure transition density and DC balance. Data is input
to each channel of the S2078 as a 10 bit wide word. An
input FIFO and a clock input, TBCx, are provided for
each channel of the S2078. The device can operate in
two different modes. The S2078 can be configured to
use either the TBCx (TBC MODE) input or the
REFCLK input (REFCLK MODE). Table 2 provides a
summary of the input modes for the S2078.

Operation in the TBC MODE makes it easier for us-
ers to meet the relatively narrow setup and hold time
window required by the 106.25 Mbps 10 bit inter-
face. The TBC signal is used to clock the data into
an internal holding register and the S2078 synchro-
nizes its internal data flow to ensure stable opera-
tion. REFCLK, not TBCx, is used as the reference
for the transmit PLL. This ensures minimum jitter on
the high speed serial data stream.

The TBC must be frequency locked to REFCLK, but
may have an arbitrary but fixed phase relationship. Ad-
justment of internal timing of the S2078 is performed
during reset. Once synchronized, the S2078 can tolerate
up to

3ns of phase drift between TBC and REFCLK.

Figure 5 demonstrates the flexibility afforded by the
S2078. A low jitter reference is provided directly to
the S2078 at either 1/10 or 1/20 the serial data rate.
This insures minimum jitter in the synthesized clock
used for serial data transmission. A system clock
output at the parallel word rate, TCLKO, is derived
from the PLL and provided to the upstream circuit as
a system clock. This clock can be buffered as re-
quired without concern about added delay. There is
no phase requirement placed upon TCLKO and the
TBCx clock, which is provided back to the S2078,

Table 1. Operating Rates

REFCLK

S2078

106.25 MHz or 53.125 MHz

TBCx

DINx[0:9]

REF

OSCILLATOR

MAC

ASIC

TCLKO

PLL

Figure 5. DIN Clocking with TBC

Table 2. Input Modes

Note that internal synchronization of FIFOs is performed upon
de-assertion of RESET.

Note: SDR = Serial Data Rate.

S2078

DUAL FIBRE CHANNEL TRANSCEIVER

June 20, 2000 / Revision B

other than that they remain within

3ns of the phase

relationship established at reset.

The S2078 also supports the traditional REFCLK
clocking found in many Fibre Channel applications
and is illustrated in Figure 6.

Half Rate Operation

The S2078 supports full and half rate operation for
all modes of operation. When RATE is LOW, the
S2078 serial data rate equals the VCO frequency.
When RATE is HIGH, the VCO is divided by 2 before
being provided to the chip. Thus the S2078 can sup-
port Fibre Channel and serial backplane functions at
both full and 1/2 the VCO rate.

Parallel to Serial Conversion

The 10-bit parallel data handled by the S2078 device
should be from a DC-balanced encoding scheme,
such as the 8B/10B transmission code, in which in-
formation to be transmitted is encoded, 8 bits at a
time, into a 10-bit transmission character and must
be compliant with ANSI X3.230 FC-PH (Fibre Chan-
nel Physical and Signaling Interface).

The 8B/10B transmission code includes serial encod-
ing and decoding rules, special characters, and error
control. Information is encoded, 8 bits at a time, into a
10 bit transmission character. The characters defined
by this code ensure that short run lengths and enough
transitions are present in the serial bit stream to make
clock recovery possible at the receiver. The encoding
also greatly increases the likelihood of detecting any

single or multiple errors that might occur during the
transmission and reception of data

Table 3 identifies the mapping of the 8B/10B charac-
ters to the data inputs of the S2078. The S2078 will
serialize the parallel data for each channel and will
transmit bit "a" or DIN[0] first.

Frequency Synthesizer (PLL)

The S2078 synthesizes a serial transmit clock from
the reference signal provided. The S2078 will obtain
phase and frequency lock within 2500 bit times after
the start of receiving reference clock inputs. Reliable
locking of the transmit PLL is assured, but a lock-
detect output is NOT provided.

Reference Clock Input

The reference clock input must be supplied with a low-
jitter clock source. All reference clocks in a system
must be within 200 ppm of each other to ensure that
the clock recovery units can lock to the serial data.

The frequency of the reference clock must be either
1/10 the serial data rate, CLKSEL = 0, or 1/20 the
serial data rate, CLKSEL = 1. Note that in both
cases, the frequency of the parallel word rate output,
TCLKO, is constant at 1/10 the serial data rate.

Serial Data Outputs

The S2078 provides LVPECL level serial outputs.
Each high speed output should be provided with a
resistor to VSS (Gnd) near the device. A value of
4.5K

provides optimal performance with minimum

impact on power dissipation. The resistance may be
as low as 450

, but will dissipate additional power

with no substantive performance improvement.

Transmit FIFO Initialization

The transmit FIFO must be initialized after stable de-
livery of data and TBC to the parallel interface, and
before entering the normal operational state of the
circuit. FIFO initialization is performed upon the de-
assertion of the RESET signal. The TCLKO output will
operate normally even when RESET is asserted and
is available for use as an upstream clock source.

]

[

]

[

Table 3. Data to 8B/10B Alphabetic Representation

1. A.X. Widner and P.A. Franaszek, "A Byte-Oriented DC Bal-
anced (0,4) 8B/10B Transmission Code," IBM Research Report
RC9391, May 1982.

REFCLK

S2078

TBCx

DINx[0:9]

REF

OSCILLATOR

MAC

ASIC

TCLKO

PLL

106.25 MHz

Figure 6. FC DIN Clocking with REFCLK

S2078

DUAL FIBRE CHANNEL TRANSCEIVER

June 20, 2000 / Revision B

RECEIVER DESCRIPTION

Each receiver channel is designed to implement the
ANSI X3T11 Fibre Channel specification. A block
diagram showing the basic function is provided in
Figure 4.

Whenever a signal is present, the receiver attempts
to recover the serial clock from the received data
stream. After acquiring bit synchronization, the
S2078 searches the serial bit stream for the occur-
rence of a K28.5 character on which to perform word
synchronization. Once synchronization on both bit
and word boundaries is achieved, the receiver pro-
vides the word-aligned data on its parallel outputs.

Data Input

A differential input receiver is provided for each
channel of the S2078. Each channel has a loopback
mode in which the serial data from the transmitter
replaces external serial data. The loopback function
for the two channels is controlled by the loopback
enable signal, LPEN.

The high speed serial inputs to the S2078 are inter-
nally biased to VDD1.3V. This facilities AC-coupling
of the differential inputs and termination with a single
differential termination. For applications in which
long periods of no data present may occur, a small
positive bias, relative to the inverting input, should
be created on the non-inverting input by connecting
a 10K

resistor to VDD. This will prevent oscillation

of the input stage during loss of input.

Clock Recovery Function

Clock recovery is provided for each channel of the
S2078. The receiver PLL has been optimized for the
needs of Fibre Channel systems. A simple state ma-
chine in the clock recovery macro decides whether to
acquire lock from the serial data input or from the
reference clock. The decision is based upon the fre-
quency and run length of the serial data inputs.

The run-length requirements insure that the S2078
will respond appropriately and quickly to a loss of
signal. The run-length checker looks for a minimum
of 120 consecutive ones or zeros. The checking is
done in parallel, thus 12 parallel words are exam-
ined.

An off-frequency detection circuit in the S2078 moni-
tors the receiver VCO frequency to insure that the
input signal is at a valid data rate. The data stream
must be within 200 ppm of the appropriate rate for
reliable locking of the CRU to the data stream.

If both the off-frequency test and the run-length test
are satisfied, the CRU will attempt to lock to the
incoming data. Note that if the run length test is sat-
isfied due to noise on the inputs, and no signal is
present, the receiver VCO will maintain frequency
accuracy to within 100 ppm of the target rate as
determined by the REFCLK.

In any transfer of PLL control from the serial data to
the reference clock, the RBC1/0x outputs remain
phase continuous and glitch free, assuring the integ-
rity of downstream clocking.

If at any time, the frequency or run length checks are
violated, the state machine forces the VCO to lock to
the reference clock. This is required to guarantee
that the VCO maintains the correct frequency in the
absence of data.

Reference Clock Input

The reference clock must be provided from a low
jitter clock source. The frequency of the received
data stream (divided by 10 or 20) must be within 200
ppm of the reference clock to insure reliable locking
of the receiver PLL. A single reference clock is pro-
vided to both the transmitter and the receiver of the
S2078.

S2078

DUAL FIBRE CHANNEL TRANSCEIVER

June 20, 2000 / Revision B

Serial-to-Parallel Conversion

Once bit synchronization has been attained by the
S2078 CRU, the S2078 must synchronize to the 10
bit word boundary. Word synchronization in the
S2078 is accomplished by detecting and aligning to
the 8B/10B K28.5 codeword. The S2078 will detect
and byte-align to either polarity of the K28.5. Each
channel of the S2078 will detect and align to a K28.5
anywhere in the data stream. The presence of a
K28.5 is indicated for each channel by the assertion
of the COM_DETx (Comma Detect) signal.

Data Output

Data is output on the DOUTx[0:9] outputs. The
COM_DETx signal is used to indicate the reception
of a valid K28.5 character and is driven concurrent
with the K28.5 character on the DOUTx[0:9] outputs.

The S2078 TTL outputs are optimized to drive 65

line impedences. Internal source matching provides
good performance on unterminated lines of reason-
able length.

Parallel Output Clock Rate

Two output clock modes are supported. When
CMODE is HIGH, a complementary TTL clock at the
data rate is provided on the RBC1/0x outputs. Data
should be clocked on the rising edge of RBC1x.
When CMODE is LOW, the S2078 outputs a
complementary TTL clock at 1/2 the data rate in
compliance with the the Fibre Channel 10 Bit Inter-
face Specification. Data should be latched on the
rising edge of RBC1x and the rising edge of RBC0x.

If consecutive K28.5 characters are received, the
S2078 RBC1/0x clock operates without glitches or
loss of cycles.

Table 4. Output Clock Modes

S2078

DUAL FIBRE CHANNEL TRANSCEIVER

June 20, 2000 / Revision B

Table 6. Transmitter Output Signals Assignment and Descriptions

]

[

]

[

Table 5. Transmitter Input Signals Assignment and Descriptions

Note: All TTL inputs except REFCLK have internal pull-up networks.

S2078

DUAL FIBRE CHANNEL TRANSCEIVER

June 20, 2000 / Revision B

Table 8. Receiver Input Signals Assignment and Descriptions

Table 7. Receiver Output Signals Assignment and Descriptions

]

[

]

[

]

[

]

[

S2078

DUAL FIBRE CHANNEL TRANSCEIVER

June 20, 2000 / Revision B

Note: All TTL inputs except REFCLK have internal pull-up networks.

]

[

Table 10. Mode Control Signal Assignment and Descriptions

Table 9. Receiver Control Signals Assignment and Descriptions

)

(

)

(

Note: All TTL inputs except REFCLK have internal pull-up networks.

S2078

DUAL FIBRE CHANNEL TRANSCEIVER

June 20, 2000 / Revision B

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

Table 11. Power and Ground Signals Assignment and Descriptions

S2078

DUAL FIBRE CHANNEL TRANSCEIVER

June 20, 2000 / Revision B

Figure 7. S2078 Pinout (Bottom View)

Note: NC used as Test Pins. Do Not Connect.

S2078

DUAL FIBRE CHANNEL TRANSCEIVER

June 20, 2000 / Revision B

Figure 8. S2078 Pinout (Top View)

Note: NC used as Test Pins. Do Not Connect.

S2078

DUAL FIBRE CHANNEL TRANSCEIVER

June 20, 2000 / Revision B

Figure 11. Transmitter Timing (TBC Mode, TMODE =1)

Table 13. S2078 Transmitter Timing (TBC Mode, TMODE =1)

TBCx

DINx[0:9]

SERIAL DATA OUT

1. All AC measurements are made from the reference voltage level of the clock (1.4V) to the valid input or output data

levels (.8V or 2.0V).

Figure 10. Transmitter Timing (REFCLK Mode, TMODE =0)

Table 12. S2078 Transmitter Timing (REFCLK Mode, TMODE = 0)

REFCLK

DINx[0:9]

SERIAL DATA OUT

1. All AC measurements are made from the reference voltage level of the clock (1.4V) to the valid input or output data

levels (.8V or 2.0V).

S2078

DUAL FIBRE CHANNEL TRANSCEIVER

June 20, 2000 / Revision B

Note: Measurements are made at 1.4V level of clocks.

Table 15. S2078 Transmitter (TCLKO Timing)

REFCLK

TCLKO

Figure 12. TCLKO Timing

Table 14. S2078 Transmitter Timing

)

(

)

(

S2078

DUAL FIBRE CHANNEL TRANSCEIVER

June 20, 2000 / Revision B

Figure 13. Receiver Timing (Full Clock Mode, CMODE = 1)

Table 16. S2078 Receiver Timing (Full Clock Mode, CMODE = 1)

Table 17. S2078 Receiver Timing (Half Clock Mode, CMODE = 0)

RBC0x

DOUTx[0:9],
COM_DETx

SERIAL DATA IN

RBC1x

1. All AC measurements are made from the reference voltage level of the clock (1.4V) to the valid input or

output data levels (.8V or 2.0V).

RBC0x

DOUTx[0:9],
COM_DETx

SERIAL DATA IN

RBC1x

1. All AC measurements are made from the reference voltage level of the clock (1.4V) to the valid input or output data

levels (.8V or 2.0V).

S2078

DUAL FIBRE CHANNEL TRANSCEIVER

June 20, 2000 / Revision B

OTHER OPERATING MODES

Loopback Mode

When loopback mode is enabled, the serial data
from the transmitter is provided to the serial input of
the receiver. Loopback mode can be simultaneously
enabled for both channels using the loopback-en-
able input, LPEN.

The loopback mode provides the ability to perform
system diagnostics and off-line testing of the inter-
face to guarantee the integrity of the serial channel
before enabling the transmission medium.

Note that the high speed outputs are disabled during
loopback operation.

Test Modes

The RESET pin is used to initialize the transmit
FIFOs and must be asserted (LOW) prior to entering
the normal operational state (see section Transmit
FIFO Initialization).

Operating Frequency Rate

The S2078 is designed to operate at the Fibre Chan-
nel rate of 1.062 GHz.

output

disabled

CRU

CSU

Figure 15. S2078 Diagnostic Loopback Operation

Table 18. S2078 Receiver Timing

)

(

)

(

S2078

DUAL FIBRE CHANNEL TRANSCEIVER

June 20, 2000 / Revision B

Table 19. Absolute Maximum Ratings

Table 20. Recommended Operating Conditions

Table 21. Reference Clock Requirements

S2078

DUAL FIBRE CHANNEL TRANSCEIVER

June 20, 2000 / Revision B

Table 22. DC Characteristics

)

(

)

(

)

(

)

(

)

(

)

(

S2078

DUAL FIBRE CHANNEL TRANSCEIVER

June 20, 2000 / Revision B

OUTPUT LOAD

The S2078 serial outputs require a resistive load to
set the output current. The recommended resistor
value is 4.5K

to ground. This value can be varied

to adjust drive current, signal voltage swing, and
power usage on the board.

ACQUISITION TIME

With the input eye diagram shown in Figure 21, the
S2078 will recover data with a

1E-9 BER within the

time specified by T

LOCK

in Table 18 after an instan-

taneous phase shift of the incoming data.

Figure 19. High Speed Differential Inputs

Figure 16. Serial Input/Output Rise and Fall Time

Figure 20. Receiver Input Eye Diagram Jitter Mask

Figure 17. TTL Input/Output Rise and Fall Time

Figure 18. Serial Output Load

Figure 21. Acquisition Time Eye Diagram

80%

20%

50%

80%

20%

50%

+2.0V

+0.8V

+2.0V

+0.8V

4.5K

0.01

Vcc 1.3V

100

0.01

Vcc 1.3 V

Bit Time

Amplitude

30%

1.3

Normalized Amplitude

Normalized Time

1.0

0.0

0.2

0.3

0.5

0.7

0.8

0.1

0.6

0.4

0.3

0.7

0.9

1.0

0.0

S2078

DUAL FIBRE CHANNEL TRANSCEIVER

June 20, 2000 / Revision B

Ordering Information

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Prefix Device Package

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