1
S2091
2.5 GBIT PORT BYPASS CIRCUIT FOR FIBRE CHANNEL ARBITRATED LOOP
S2091
2.5 GBIT PORT BYPASS CIRCUIT FOR FIBRE CHANNEL ARBITRATED LOOP
FEATURES
Supports 2.5 Gbps Data Rates
Fully differential for minimum
jitter accumulation
TTL Bypass Select
High speed 50
source terminated outputs
0.4W Typical power dissipation
3.3V power supply
20 Pin TSSOP
GENERAL DESCRIPTION
The S2091 is a Port Bypass Circuit (PBC). A single
channel Fibre Channel PBC offers designers maxi-
mum flexibility in FC-AL disk architectures. The
S2091 is designed to minimize jitter accumulation by
providing a high bandwidth fully differential signal
path. Port Bypass circuits are used to provide resil-
iency in Fibre Channel Arbitrated Loop (FC-AL) ar-
chitectures. PBC's are used within FC-AL disk arrays
to allow for resiliency and hot swapping of FC-AL
drives.
A Port-by-Pass Circuit is a 2:1 Multiplexer with two
modes of operations: Normal and Bypass. In Normal
mode, the disk drive is connected to the loop. In
Bypass mode, the disk drive is either absent or non-
OUT P/N
SEL
DDI P/N
DDO P/N
IN P/N
1
0
PBC
Figure 1. S2091 Block Diagram
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Table 1. Truth Table
functional and data bypasses to the next available disk
drive. Normal mode is enabled with a High on the SEL
pin and Bypass mode is enable by a Low on the SEL
pin. Direct Attach Fibre Channel Disk Drives have an
"LRC Interlock" signal defined to control the SEL func-
tion. A system diagram showing the S2091 in a single
loop of a disk array is illustrated in Figure 2.
The S2091 can be cascaded with the S3040 (Data
retimer) for arrays of disk drives greater than 4.
Table 1 is a truth table detailing the data flow
through the S2091. Figure 3 shows a timing diagram
of the data relationship in the S2091. The primary
AC parameter of importance is the deterministic jitter
or data eye degradation inserted by the port bypass
circuit. The design for the S2091 minimized jitter ac-
cumulation by using high bandwidth, low skew fully
differential circuits. This provides for symmetric rise
and fall delays as well as noise rejection.
DEVICE
SPECIFICATION
3
S2091
2.5 GBIT PORT BYPASS CIRCUIT FOR FIBRE CHANNEL ARBITRATED LOOP
Figure 3. Timing Waveforms
Figure 4. Differential Voltage
IN P/N
DI P/N
OUT P/N
DO P/N
T
1, 2, 3
V
P-P
= 2 x single-ended swing
Single-ended swing
4
2.5 GBIT PORT BYPASS CIRCUIT FOR FIBRE CHANNEL ARBITRATED LOOP
S2091
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Table 2. Pin Assignment and Descriptions
Figure 5. S2091 Pinout Package
20
VCC
19
DDOP
18
DDON
17
VCC
16
GND
15
OUTP
14
OUTN
13
GND
12
VCC
11
SEL
VCC
1
VCC
2
DDIN
3
DDIP
4
GND
5
INN
6
INP
7
GND
8
GND
9
VCC
10
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