S2092

SERIAL BACKPLANE RETIMER DEVICE

July 10, 2000 / Revision A

BiCMOS PECL CLOCK GENERATOR

DEVICE
SPECIFICATION

SERIAL BACKPLANE RETIMER DEVICE

S2092

FEATURES

On-chip high frequency PLL with internal
loop filter for clock recovery

Internal 100

line-to-line termination on

high speed differential input

Supports data recovery from:

2.488 to 2.67 Gbps (2.488 Gbps with FEC

overhead data rate capability)

Selectable reference frequencies

Lock detect--monitors frequency of
incoming data

Low-jitter serial CML interface

Single +3.3 V supply, 455 mW power
dissipation (typ)

Compact 7 mm x 7 mm 48 pin TQFP/TEP
package

APPLICATIONS

Dense Wavelength Division Multiplexing
(DWDM) systems

Serial Backplane interfaces

2.488 Gbps to 2.67 Gbps Short Haul
Retiming

Crosspoint interfaces

GENERAL DESCRIPTION

The function of the S2092 retimer device is to derive
high speed timing signals for DWDM equipment. The
S2092 is implemented using AMCC's proven Phase
Lock Loop (PLL) technology. Figure 1 shows a typical
network application.

The S2092 can receive a 2.488 Gbps to 2.67 Gbps
scrambled NRZ signal. This range is dependent on
the user's FEC needs and reference frequency selec-
tion. The S2092 recovers the clock from the data
and outputs the retimed data.

The S2092 utilizes an on-chip PLL which consists
of a phase detector, a loop filter, and a Voltage
Controlled Oscillator (VCO). The phase detector
compares the phase relationship between the VCO
output and the serial data input. A loop filter con-
verts the phase detector output into a smooth DC
voltage, and the DC voltage is input to the VCO
whose frequency is varied by this voltage. A block
diagram is shown in Figure 2.

Figure 1. System Block Diagram

S3057

S3052

S3057

S3056

Port Card

S2018

Switch Card

S2092

S3057

S3052

S3057

S3052

S3057

S3056

Port Card

S3052

S3056

S3057

S3052

S2092

SERIAL BACKPLANE RETIMER DEVICE

July 10, 2000 / Revision A

S2092 OVERVIEW

The S2092 supports clock recovery from 2.488 Gbps
to 2.67 Gbps data rate. Differential serial data is input
to the chip at the specified rate, and clock recovery is
performed on the incoming data stream. An external
oscillator is required to minimize the PLL lock time.
Retimed data is output from the S2092.

Figure 2. S2092 Functional Block Diagram

LOCKDET

SERDATOP/N

REFCLKP/N

TESTCLK

LCKREFN

SERDATIP/N

LOOP

FILTER

VCO

CLOCK

DIVIDER

PHASE DETECTOR

LOCK

DETECTOR

SDN

CAP 1,2

REFSEL

TESTEN

RST

BYPASS

TESTOUT 1

TESTOUT 2

Suggested Interface Devices

S2092

SERIAL BACKPLANE RETIMER DEVICE

July 10, 2000 / Revision A

S2092 FUNCTIONAL DESCRIPTION

The S2092 retimer device performs clock recovery
function from 2.488 Gbps to 2.67 Gbps serial data
links. The chip extracts the clock from the serial data
inputs and provides retimed data outputs. A 155.52
to 166.63 or 19.44 to 20.83 MHz reference clock is
required (REFCLK frequency is dependent on which
FEC capability is required. See Table 2 for the
number of bytes per 255 byte block to set the proper
reference frequency.) for phase lock loop start up
and proper operation under loss of signal conditions.
An integral prescaler and phase lock loop circuit is
used to multiply this reference to the nominal bit rate.

Data Retiming

Data retiming, as shown in the block diagram in Fig-
ure 2, generates a clock that is at the same fre-
quency as the incoming data bit rate at the serial
data input. The clock is phase aligned by a PLL so
that it samples the data in the center of the data eye
pattern.

The phase relationship between the edge transi-
tions of the data and those of the generated clock
are compared by a phase/frequency discriminator.
Output pulses from the discriminator indicate the
required direction of phase corrections. These
pulses are smoothed by an integral loop filter. The
output of the loop filter controls the frequency of
the Voltage Controlled Oscillator (VCO), which
generates the recovered clock.

Table 1. Reference Frequency Select

Frequency stability without incoming data is guaran-
teed by an alternate reference input (REFCLK) that
the PLL locks onto when data is lost. If the frequency
of the incoming signal varies by a value greater than
that stated in Table 7 with respect to REFCLKP/N,
the PLL will be declared out of lock, and the PLL will
lock to the reference clock. The assertion of SDN will
also cause an out of lock condition.

The loop filter transfer function is optimized to enable
the PLL to track the jitter, yet tolerate the minimum
transition density in a received data signal.

Lock Detect

The S2092 contains a lock detect circuit which monitors
the integrity of the serial data inputs. If the received
serial data fails the frequency test, the PLL will be
forced to lock to the local reference clock. This will
maintain the correct frequency of the recovered clock
output under loss of signal or loss of lock conditions. If
the recovered clock frequency deviates from the local
reference clock frequency by more than that stated in
Table 7, the PLL will be declared out of lock. The lock
detect circuit will poll the input data stream in an attempt
to reacquire lock to data. If the recovered clock fre-
quency is determined to be within that range stated in
Table 7, the PLL will be declared in lock and the lock
detect output will go active. The assertion of SDN will
also cause an out of lock condition.

Table 2. FEC Modes

S2092

SERIAL BACKPLANE RETIMER DEVICE

July 10, 2000 / Revision A

CHARACTERISTICS

Input Jitter Tolerance

Input jitter tolerance is defined as the peak to
peak amplitude of sinusoidal jitter applied on the
input signal that causes an equivalent 1 dB opti-
cal/electrical power penalty. See Figure 3.

Jitter Transfer

The jitter transfer function is defined as the ratio of
jitter on the output signal to the jitter applied on the
input signal versus frequency. Jitter transfer require-
ments are shown in Figure 4. The measurement con-
dition is that input sinusoidal jitter up to the mask
level in Figure 4 be applied.

Jitter Generation

The jitter of the serial data outputs shall not exceed
the value specified in Table 7. The conditions are
stated with a serial data input with no jitter presented
on SERDATIP/N. (See Table 7).

Figure 3. Input Jitter Tolerance Specification

Figure 4. Jitter Transfer Specification

0.15

1.5

Sinusodal

Input Jitter

Amplitude

(UI p-p)

Jitter

Transfer

Frequency

Acceptable

Range

slope = -20 dB/decade

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)

(

)

(

S2092

SERIAL BACKPLANE RETIMER DEVICE

July 10, 2000 / Revision A

Table 3. Pin Assignment and Descriptions

3
2

)

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6
7

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S2092

SERIAL BACKPLANE RETIMER DEVICE

July 10, 2000 / Revision A

Table 5. Recommended Operating Conditions

Table 4. Absolute Maximum Ratings

)

(

Table 6. Reference Clock Requirements

Electrostatic Discharge (ESD) Ratings
The S2092 is rated to the following ESD voltages based on the human body model:
1. All pins are rated at 1500 V except pins 24, 37, 38, 41, 42, and 43.
2. Pins 24, 37, 38, 41, 42, and 43 are rated at 100 V.

S2092

SERIAL BACKPLANE RETIMER DEVICE

July 10, 2000 / Revision A

Table 8. CML Input DC Characteristics

Table 7. Serial Data Timing, Input (SERDATIP/N), Output (SERDATOP/N)

)

(

)

(

)

S2092

SERIAL BACKPLANE RETIMER DEVICE

July 10, 2000 / Revision A

Table 10. LVTTL, LVPECL DC Characteristics

)

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(

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(

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Note: All parameters are specified with respect to the source termination and ground with V

TTL

= Max. = 3.47 V.

Table 9. CML Output DC Characteristics

S2092

SERIAL BACKPLANE RETIMER DEVICE

July 10, 2000 / Revision A

Table 11. Internally Biased Differential LVPECL Input Characteristics

Figure 7. Differential Voltage Measurement

Note: V(+) V(-) is the algebraic difference of the input signals.

V(+)

V()

V(+) V(-)

0.0V

VSWING

VD = 2 X VSWING

S2092

SERIAL BACKPLANE RETIMER DEVICE

July 10, 2000 / Revision A

Ordering Information

XXXX

Prefix Device Package

AMCC is a registered trademark of Applied Micro Circuits Corporation.

D44/R111

AMCC reserves the right to make changes to its products or to discontinue any semiconductor product or service without notice, and
advises its customers to obtain the latest version of relevant information to verify, before placing orders, that the information being relied
on is current.

AMCC does not assume any liability arising out of the application or use of any product or circuit described herein, neither does it
convey any license under its patent rights nor the rights of others.

AMCC reserves the right to ship devices of higher grade in place of those of lower grade.

AMCC SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR
USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS.

Applied Micro Circuits Corporation · 6290 Sequence Dr., San Diego, CA 92121

Phone: (858) 450-9333 · (800)755-2622 · Fax: (858) 450-9885

http://www.amcc.com

R T I F I E

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