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Электронный компонент: S2102

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S2102
DUAL FIBRE CHANNEL DEVICE
July 14, 1999 / Revision A
S2102
DUAL FIBRE CHANNEL DEVICE
DEVICE
SPECIFICATION
MAC
(ASIC)
S2002
DUAL
FIBRE
CHANNEL
INTERFACE
MAC
(ASIC)
TO SERIAL BACKPLANE
S2102
FC INTERFACE
SERIAL BP DRIVER
Figure 1. Typical Dual Fibre Channel Application
FEATURES
1062 MHz (Fibre Channel) operating rate
- Half rate operation
Dual Transmitter with phase-locked loop (PLL)
clock synthesis from low speed reference
Dual Receiver PLL provides clock and data
recovery
Internally series terminated TTL outputs
Low-jitter serial PECL interface
Individual local loopback control
JTAG 1149.1 Boundary scan on low speed I/O
signals
Interfaces with coax, twinax, or fiber optics
Single +3.3V supply, 1.85 W power dissipation
Compact 21mm x 21mm 156 TBGA package
APPLICATIONS
Workstation
Frame buffer
Switched networks
Data broadcast environments
Proprietary extended backplanes
GENERAL DESCRIPTION
The S2102 facilitates high-speed serial transmission
of data in a variety of applications including Fibre
Channel, serial backplanes, and proprietary point to
point links. The chip provides two separate trans-
ceivers which are operated individually for a data
capacity of >2 Gbps.
Each bi-directional channel provides parallel to serial
and serial to parallel conversion, clock generation/
recovery, and framing. The on-chip transmit PLL
synthesizes the high-speed clock from a low-speed
reference. The on-chip dual receive PLL is used for
clock recovery and data re-timing on the two inde-
pendent data inputs. The transmitter and receiver
each support differential PECL-compatible I/O for
copper or fiber optic component interfaces with ex-
cellent signal integrity. Local loopback mode allows
for system diagnostics. The chip requires a 3.3V
power supply and dissipates 1.85 watts.
Figure 1 shows the S2102 and S2002 in a Fibre
Channel application. Figure 2 summarizes the in-
put/output signals of the device. Figures 3 and 4
show the transmit and receive block diagrams, re-
spectively.
2
DUAL FIBRE CHANNEL DEVICE
S2102
July 14, 1999 / Revision A
Figure 2. S2102 Input/Output Diagram
REFCLK
RATE
RESET
TCLKO
TXAP/N
TXBP/N
RXAP/N
RXBP/N
DINA[0:9]
10
DINB[0:9]
10
TBCA
TBCB
10
RBC1/0A
10
RBC1/0B
DOUTA[0:9]
DOUTB[0:9]
CLKSEL
TMODE
COM_DETA
COM_DETB
CMODE
TESTMODE2
LPENA
LPENB
TRS
TMS
TCK
TDI
TDO
TESTMODE1
TESTMODE
3
S2102
DUAL FIBRE CHANNEL DEVICE
July 14, 1999 / Revision A
Figure 3. Transmitter Block Diagram
10
DINA[0:9]
TMODE
DINB[0:9]
10
Shift
Reg
10
10
Shift
Reg
DIN PLL
10x/20x
REFCLK
CLKSEL
RATE
REFCLK
TCLKO
FIFO
(input)
FIFO
(input)
TBCA
TBCB
TXAP
TXAN
TXABP
TXBP
TXBN
TXBBP
0 1
0 1
TMODE
4
DUAL FIBRE CHANNEL DEVICE
S2102
July 14, 1999 / Revision A
Figure 4. Receiver Block Diagram
DOUT CRU
Serial-
Parallel
DOUT CRU
Serial-
Parallel
COM_DETA
DOUTA[0:9]
RXAP
RXAN
LPENA
RXBP
RXBN
LPENB
COM_DETB
RBC1/0A
RBC1/0B
DOUTB[0:9]
Q
FIFO
(output)
TXBBP
TXABP
REFCLK
10
2
10
CMODE
RATE
TMODE
FIFO
(output)
10
10
2
5
S2102
DUAL FIBRE CHANNEL DEVICE
July 14, 1999 / Revision A
Figure 5. DIN Data Clocking with TBC
TRANSMITTER DESCRIPTION
The transmitter section of the S2102 contains a single
PLL which is used to generate the serial rate transmit
clock for all transmitters. Two channels are provided
with a variety of options regarding input clocking and
loopback. The transmitters operate at 1.062 GHz, 10
or 20 times the reference clock frequency.
Data Input
The S2102 has been designed to simplify the parallel
interface data transfer and provides the utmost in flex-
ibility regarding clocking of parallel data. The S2102
incorporates a unique FIFO structure on both the par-
allel inputs and the parallel outputs which enables the
user to provide a "clean" reference source for the PLL
and to accept a separate external clock which is used
exclusively to reliably clock data into the device. Data
can also be clocked in using the REFCLK.
Data is input to each channel of the S2102 nominally
as a 10 bit wide word. An input FIFO and a clock
input, TBCx, are provided for each channel of the
S2102. The device can operate in two different
modes. The S2102 can be configured to use either
the TCLKx (TCLK MODE) input or the REFCLK input
(REFCLK MODE). In TCLK or REFCLK mode, 10
bits of data are clocked into its FIFO with the TBCx
provided with each 10 bits. Table 1 provides a sum-
mary of the input modes of the S2102.
Operation in the TBC MODE makes it easier for us-
ers to meet the relatively narrow setup and hold time
window required by the 106.25 Mbps 10-bit inter-
face. The TBC signal is used to clock the data into
an internal holding register and the S2102 synchro-
nizes its internal data flow to ensure stable opera-
tion. However, regardless of the clock mode,
REFCLK is always the VCO reference clock. This
facilitates the provision of a clean reference clock
resulting in minimum jitter on the serial output. The
TBC must be frequency locked to REFCLK, but may
have an arbitrary phase relationship. Adjustment of
internal timing of the S2102 is performed during re-
set. Once synchronized, the user must ensure that
the timing of the TBC signal does not change by
more than
3 ns relative to the REFCLK.
Figure 5 demonstrates the flexibility afforded by the
S2102. A low jitter reference is provided directly to
the S2102 at either 1/10 or 1/20 the serial data rate.
This ensures minimum jitter in the synthesized clock
used for serial data transmission. A system clock
output at the parallel word rate, TCLKO, is derived
from the PLL and provided to the upstream circuit as
a system clock. The frequency of this output is con-
stant at the parallel word rate, 1/10 the serial data
Figure 6. FC DIN Clocking with REFCLK
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Table 1. Input Modes
REFCLK
S2102
106.25 MHz or 53.125 MHz
TBCx
DINx[0:9]
REF
OSCILLATOR
MAC
ASIC
TCLKO
PLL
REFCLK
S2102
TBCx
DINx[0:9]
REF
OSCILLATOR
MAC
ASIC
TCLKO
PLL
106.25 MHz
Note that internal synchronization of FIFOs is performed upon
de-assertion of RESET.
6
DUAL FIBRE CHANNEL DEVICE
S2102
July 14, 1999 / Revision A
Table 3. Operating Rates
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rate, regardless of whether the reference is provided
at 1/10 or 1/20 the serial data rate. This clock can be
buffered as required without concern about added
delay. There is no phase requirement between
TCLKO and TBCx, which is provided back to the
S2102, other than that they remain within
3ns of
the phase relationship established at reset.
The S2102 also supports the traditional REFCLK
clocking found in many Fibre Channel applications
and is illustrated in Figure 6.
Half Rate Operation
The S2102 supports full and half rate operation for
all modes of operation. When RATE is LOW, the
S2102 serial data rate equals the VCO frequency.
When RATE is HIGH, the VCO is divided by 2 before
being provided to the chip. Thus the S2102 can sup-
port Fibre Channel and serial backplane functions at
both full and half the VCO rate. See Table 3.
Parallel to Serial Conversion
The 10-bit parallel data handled by the S2102 device
should be from a DC-balanced encoding scheme,
such as the 8B/10B transmission code, in which in-
formation to be transmitted is encoded, 8 bits at a
time, into a 10-bit transmission character and must
be compliant with ANSI X3.230 FC-PH (Fibre Chan-
nel Physical and Signaling Interface).
The 8B/10B transmission code includes serial en-
coding and decoding rules, special characters, and
error control. Information is encoded, 8 bits at a time,
into a 10 bit transmission character. The characters
defined by this code ensure that short run lengths
and enough transitions are present in the serial bit
stream to make clock recovery possible at the re-
ceiver. The encoding also greatly increases the like-
lihood of detecting any single or multiple errors that
might occur during the transmission and reception of
data
1
.
Table 2 identifies the mapping of the 8B/10B charac-
ters to the data inputs of the S2102. The S2102 will
serialize the parallel data for each channel and will
transmit bit "a" or DIN[0] first.
Frequency Synthesizer (PLL)
The S2102 synthesizes a serial transmit clock from
the reference signal. Upon startup, the S2102 will
obtain phase and frequency lock within 2500 bit
times after the start of receiving reference clock in-
puts. Reliable locking of the transmit PLL is assured,
but a lock-detect output is NOT provided.
Reference Clock Input
The reference clock input must be supplied with a
low-jitter clock source. All reference clocks in a sys-
tem must be within 200 ppm of each other to ensure
that the clock recovery units can lock to the serial
data.
The frequency of the reference clock must be either
1/10 the serial data rate, CLKSEL = 0, or 1/20 the
serial data rate, CLKSEL=1. In both cases the fre-
quency of the parallel word rate output, TCLKO, is
constant at 1/10 the serial data rate. See Table 3.
Serial Data Outputs
The S2102 provides LVPECL level serial outputs.
The serial outputs do not require output pulldown
resistors. Outputs are designed to perform optimally
when AC-coupled.
Transmit FIFO Initialization
The transmit FIFO must be initialized after stable
delivery of data and TBC to the parallel interface,
and before entering the normal operational state of
the circuit. FIFO initialization is performed upon the
de-assertion of the RESET signal. TCLKO will oper-
ate normally regardless of the state of RESET.
1. A.X. Widner and P.A. Franaszek, "A Byte-Oriented DC Bal-
anced (0,4) 8B/10B Transmission Code," IBM Research Report
RC9391, May 1982.
Table 2. Data to 8B/10B Alphabetic Representation
7
S2102
DUAL FIBRE CHANNEL DEVICE
July 14, 1999 / Revision A
RECEIVER DESCRIPTION
Each receiver channel is designed to implement a
Serial Backplane receiver function through the physi-
cal layer. A block diagram showing the basic func-
tion is provided in Figure 4.
Whenever a signal is present, the receiver attempts
to recover the serial clock from the received data
stream. After acquiring bit synchronization, the
S2102 searches the serial bit stream for the occur-
rence of a K28.5 character on which to perform word
synchronization. Once synchronization on both bit
and word boundaries is achieved, the receiver pro-
vides the word-aligned data on its parallel outputs.
Data Input
A differential input receiver is provided for each
channel of the S2102. Each channel has a loopback
mode in which the serial data from the transmitter
replaces external serial data. The loopback function
for each channel is enabled by its respective LPEN
input.
The high speed serial inputs to the S2102 are inter-
nally biased to VDD-1.3V. All that is required exter-
nally are AC-coupling and line-to-line differential
termination.
Clock Recovery Function
Clock recovery is performed on the input data
stream for each channel of the S2102. The receiver
PLL has been optimized for the anticipated needs of
Serial Backplane systems. A simple state machine in
the clock recovery macro decides whether to acquire
lock from the serial data input or from the reference
clock. The decision is based upon the frequency and
run length of the serial data inputs. If at any time the
frequency or run length checks are violated, the
state machine forces the VCO to lock to the refer-
ence clock. This allows the VCO to maintain the cor-
rect frequency in the absence of data.
The "lock to reference" frequency criteria ensure that
the S2102 will respond to variations in the serial data
input frequency (compared to the reference fre-
quency). The new lock state is dependent upon the
current lock state, as shown in Table 4.
The run-length criteria ensure that the S2102 will
respond appropriately and quickly to a loss of signal.
The run-length checker flags a condition of consecu-
tive ones or zeros across 12 parallel words. Thus
119 or less consecutive ones or zeros does not
cause signal loss, 129 or more causes signal loss,
and 120 - 128 may or may not, depending on how
the data aligns across byte boundaries.
If both the off-frequency detect circuitry test and the
run-length test are satisfied, the CRU will attempt to
lock to the incoming data. It is possible for the run
length test to be satisfied due to noise on the inputs,
even if no signal is present. In this case the receiver
VCO will maintain frequency accuracy to within 100
ppm of the target rate as determined by REFCLK.
In any transfer of PLL control from the serial data to
the reference clock, the RBC1/0x outputs remain
phase continuous and glitch free, assuring the integ-
rity of downstream clocking.
Reference Clock Input
A single reference clock, which serves both transmit-
ter and receiver, must be provided from a low jitter
clock source. The frequency of the received data
stream (divided-by-10 or -20) must be within 200
ppm of the reference clock to ensure reliable locking
of the receiver PLL.
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Table 4. Lock to Reference Frequency Criteria
8
DUAL FIBRE CHANNEL DEVICE
S2102
July 14, 1999 / Revision A
Figure 7. S2102 Diagnostic Loopback Operation
CRU
CSU
OTHER OPERATING MODES
Operating Frequency Rate
The S2102 is designed to operate at the Fibre Chan-
nel rate of 1.062 GHz.
Loopback Mode
When loopback mode is enabled, the serial data
from the transmitter is provided to the serial input of
the receiver, as shown in Figure 7. This provides the
ability to perform system diagnostics and off-line
testing of the interface to verify the integrity of the
serial channel. Loopback mode is enabled indepen-
dently for each channel using its respective
loopback-enable input, LPEN.
Test Modes
The RESET pin is used to initialize the Transmit
FIFOs and must be asserted (LOW) prior to entering
the normal operational state (see section Transmit
FIFO Initialization).
Note: Serial output data remains active during loopback opera-
tion to enable other system tests to be performed.
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Table 5. Output Clock Mode
Serial to Parallel Conversion
Once bit synchronization has been attained by the
S2102 CRU, the S2102 must synchronize to the 10
bit word boundary. Word synchronization in the
S2102 is accomplished by detecting and aligning to
the 8B/10B K28.5 codeword. The S2102 will detect
and byte-align to either polarity of the K28.5. Each
channel of the S2102 will detect and align to a K28.5
anywhere in the data stream. For TCLK ot REFCLK
mode operation, the presence of a K28.5 is indicated
for each channel by the assertion of the COM_DETx
signal.
Data Output
Data is output on the DOUT[0:9] outputs. The
COM_DETx signal is used to indicate the reception of
a valid K28.5 character.
The S2102 TTL outputs are optimized to drive 65
line impedances. Internal source matching provides
good performance on unterminated lines of reason-
able length.
Parallel Output Clock Rate
Two output clock modes are supported, as shown in
Table 5. When CMODE is High, a complementary
TTL clock at the data rate is provided on the RBC1/0x
outputs. Data should be clocked on the rising edge of
RBC1x. When CMODE is Low, a complementary TTL
clock at half the data rate is provided. Data should be
latched on the rising edge of RBC1x and the rising
edge of RBC0x.
In Fibre Channel applications, multiple consecutive
K28.5 characters cannot be generated. However, for
serial backplane applications this can occur. The
S2102 must be able to operate properly when mul-
tiple K28.5 characters are received. After the first
K28.5 is detected and aligned, the RBC1/0x clock
will operate without glitches or loss of cycles.
External Receiver Clocking
An external clock can be provided to the S2102 to
clock the parallel receive data, DOUT[0:9], out of the
device. External Clock mode is enabled when
TMODE = Low. Table 5A describes the receiver out-
put clocking options available. When TBCA is used
as the output clock source, the REFCLK and TBCA
frequency must equal the parallel word rate,
CLKSEL = Low. The RBC1/0x outputs will provide a
buffered copy of the output clock.
Table 5A. S2102 Data Clocking
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9
S2102
DUAL FIBRE CHANNEL DEVICE
July 14, 1999 / Revision A
JTAG TESTING
The JTAG implementation for the S2102 is compli-
ant with the IEEE1149.1 requirements. JTAG is used
to test the connectivity of the pins on the chip. The
TAP, (Test Access Port), provides access to the test
logic of the chip. When TRST is asserted the TAP is
initialized. TAP is a state machine that is controlled
by TMS. The test instruction and data are loaded
through TDI on the rising edge of TCK. When TMS is
high the test instruction is loaded into the instruction
register. When TMS is low the test data is loaded
into the data register. TDO changes on the falling
edge of TCK. All input pins, including clocks, that
have boundary scan are observe only. They can be
sampled in either normal operational or test mode.
All output pins that have boundary scan, are observe
and control. They can be sampled as they are driven
out of the chip in normal operational mode, and they
can be driven out of the chip in test mode using the
Extest instruction. Since JTAG testing operates only
on digital signals there are some pins with analog
signals that JTAG does not cover. The JTAG imple-
mentation has the three required instruction, Bypass,
Extest, and Sample/Preload.
Instruction
Code
BYPASS
11
EXTEST
00
SAMPLE/PRELOAD
01
ID CODE
10
JTAG Instruction Description:
The BYPASS register contains a single shift-register
stage and is used to provide a minimum-length serial
path between the TDI and TDO pins of a component
when no test operation of that component is re-
quired. This allows more rapid movement of test
data to and from other components on a board that
are required to perform test operations.
The EXTEST instruction allows testing of off-chip cir-
cuitry and board level interconnections. Data would
typically be loaded onto the latched parallel outputs
of boundary-scan shift-register stages using the
SAMPLE/PRELOAD instruction prior to selection of
the EXTEST instruction.
The SAMPLE/PRELOAD instruction allows a snap-
shot of the normal operation of the component to be
taken and examined. It also allows data values to be
loaded onto the latched parallel outputs of the
boundary-scan shift register prior to selection of the
other boundary-scan test instructions.
The following table provides a list of the pins that are
JTAG tested. Each port has a boundary scan regis-
ter (BSR), unless otherwise noted. The following fea-
tures are described: the JTAG mode of each register
(input, output2, or internal (refers to an internal pack-
age pin)), the direction of the port if it has a bound-
ary scan register (in or out), and the position of this
register on the scan chain.
10
DUAL FIBRE CHANNEL DEVICE
S2102
July 14, 1999 / Revision A
Table 6. JTAG Pin Assignments
2
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11
S2102
DUAL FIBRE CHANNEL DEVICE
July 14, 1999 / Revision A
e
m
a
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n
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P
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v
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L
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#
n
i
P
n
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9
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T
Table 7. Transmitter Input Pin Assignment and Descriptions
12
DUAL FIBRE CHANNEL DEVICE
S2102
July 14, 1999 / Revision A
Table 9. Mode Control Signals
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Table 8. Transmitter Output Signals
e
m
a
N
n
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P
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#
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f
Note: All TTL inputs except REFCLK have internal pull-up networks.
13
S2102
DUAL FIBRE CHANNEL DEVICE
July 14, 1999 / Revision A
Table 10. Receiver Output Pin Assignment and Descriptions
e
m
a
N
n
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P
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#
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R
14
DUAL FIBRE CHANNEL DEVICE
S2102
July 14, 1999 / Revision A
Table 13. Power and Ground Signals
Table 11. Receiver Input Pin Assignment and Descriptions
e
m
a
N
n
i
P
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v
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L
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3
.
1
-
Table 12. Receiver Control Signals
e
m
a
N
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e
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1
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1
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)
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e
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.
)
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S
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(
d
n
u
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9
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6
C
,
2
1
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.
)
D
D
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(
y
r
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c
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w
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B
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8
,
2
1
A
,
1
1
A
,
7
A
,
7
B
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5
B
,
4
1
A
2
1
C
,
7
C
.
)
S
S
V
(
y
r
t
i
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c
r
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C
d
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e
p
S
h
g
i
H
r
o
f
d
n
u
o
r
G
15
S2102
DUAL FIBRE CHANNEL DEVICE
July 14, 1999 / Revision A
e
m
a
N
n
i
P
.
y
t
Q
#
n
i
P
n
o
i
t
p
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r
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s
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D
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W
P
L
C
E
P
4
,
4
1
G
,
5
1
F
,
5
1
D
5
1
H
)
D
D
V
(
r
e
w
o
P
L
C
E
P
D
N
G
L
C
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P
2
6
1
C
6
1
J
)
S
S
V
(
d
n
u
o
r
G
L
C
E
P
R
W
P
G
I
D
6
,
2
D
,
1
C
,
2
B
9
P
,
1
N
,
5
1
J
)
D
D
V
(
r
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w
o
P
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t
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G
G
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8
,
2
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1
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,
3
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1
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1
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,
3
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1
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,
1
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)
S
S
V
(
d
n
u
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G
y
r
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T
8
,
1
H
,
3
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,
1
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,
4
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1
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2
M
7
T
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8
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)
D
D
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(
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T
T
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3
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3
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2
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2
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8
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4
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2
T
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(
O
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T
T
r
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f
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e
w
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5
,
3
1
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6
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6
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1
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d
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r
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1
P
A
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2
P
A
C
2
5
1
A
4
1
B
r
o
t
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c
a
p
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c
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t
li
f
p
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l
l
a
n
r
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t
x
e
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o
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s
n
i
P
C
N
8
1
,
9
B
,
6
B
,
5
A
,
1
A
,
5
1
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,
5
C
,
6
1
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,
5
1
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4
1
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4
1
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,
2
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,
5
1
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4
1
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6
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1
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1
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9
T
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t
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e
n
n
o
C
t
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N
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D
.
s
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p
t
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e
t
s
a
d
e
s
U
.
d
e
t
c
e
n
n
o
C
t
o
N
Table 13. Power and Ground Signals (Continued)
16
DUAL FIBRE CHANNEL DEVICE
S2102
July 14, 1999 / Revision A
e
m
a
N
n
i
P
l
e
v
e
L
O
/
I
#
n
i
P
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.
t
e
s
e
R
t
s
e
T
Table 14. JTAG Test Signals
17
S2102
DUAL FIBRE CHANNEL DEVICE
July 14, 1999 / Revision A
Figure 8. S2102 Pinout (Bottom View)
A
B
C
D
E
F
G
H
J
K
L
M
N
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1
C
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9
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9
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D
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C
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C
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1
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M
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C
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A
N
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D
A
C
B
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C
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1
1
S
S
V
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C
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4
A
N
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D
2
A
N
I
D
D
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G
G
I
D
2
1
B
U
S
S
S
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D
D
V
B
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7
A
N
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5
A
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D
1
A
N
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D
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1
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D
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M
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A
D
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A
S
S
V
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G
8
A
N
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D
3
A
N
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D
4
1
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S
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2
P
A
C
A
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P
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C
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C
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C
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C
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P
R
W
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B
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P
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L
C
F
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9
B
N
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D
6
B
N
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D
3
B
N
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C
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6
A
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5
1
1
P
A
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C
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C
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P
R
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P
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7
B
N
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N
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A
N
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1
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P
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8
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B
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2
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D
0
B
N
I
D
D
N
G
Note: NC used as Test Pins. Do Not Connect.
18
DUAL FIBRE CHANNEL DEVICE
S2102
July 14, 1999 / Revision A
Figure 9. S2102 Pinout (Top View)
T
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
D
N
G
G
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D
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1
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6
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4
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2
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8
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T
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5
A
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2
2
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3
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2
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R
4
6
B
T
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3
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T
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1
B
T
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C
N
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C
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5
C
N
5
B
T
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4
B
T
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6
R
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P
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1
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P
L
2
P
A
C
S
S
V
4
1
9
A
N
I
D
C
N
1
B
N
I
D
4
B
N
I
D
7
B
N
I
D
T
S
E
T
1
E
D
O
M
O
K
L
C
T
R
W
P
G
I
D
L
C
E
P
R
W
P
C
N
L
C
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P
R
W
P
C
N
L
C
E
P
R
W
P
C
N
T
E
S
E
R
1
P
A
C
5
1
D
N
G
0
B
N
I
D
2
B
N
I
D
5
B
N
I
D
8
B
N
I
D
D
N
G
D
N
G
G
I
D
D
N
G
L
C
E
P
O
D
T
P
B
X
T
N
B
X
T
N
A
X
T
P
A
X
T
D
N
G
L
C
E
P
C
N
R
W
P
6
1
Note: NC used as Test Pins. Do Not Connect.
19
S2102
DUAL FIBRE CHANNEL DEVICE
July 14, 1999 / Revision A
Figure 10. Compact 21mm x 21mm 156 TBGA Package
Device
S2102
15C/W
ja
1.0C/W
jc
Thermal Management
20
DUAL FIBRE CHANNEL DEVICE
S2102
July 14, 1999 / Revision A
s
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3
-
3
+
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n
TBCx
DINx[0:9]
T
1
T
2
SERIAL DATA OUT
Figure 12. Transmitter Timing (TBC Mode, TMODE = 1 )
Table 16. S2102 Transmitter Timing (TBC Mode, TMODE = 1)
1. All AC measurements are made from the reference voltage levels of the clock (1.4V) to the valid input or output data
levels (.8V or 2.0V).
Figure 11. Transmitter Timing (REFCLK Mode, TMODE = 0)
Table 15. S2102 Transmitter Timing (REFCLK Mode, TMODE = 0)
1. All AC measurements are made from the reference voltage levels of the clock (1.4V) to the valid input or output data
levels (.8V or 2.0V).
REFCLK
DINx[0:9]
T
1
T
2
SERIAL DATA OUT
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1
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a
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D
5
.
1
-
s
n
--
21
S2102
DUAL FIBRE CHANNEL DEVICE
July 14, 1999 / Revision A
Table 17. S2102 Receiver Timing (Full and Half Clock Mode)
1. Measurements made from the reference voltage levels of the clock (1.4V) to the valid input or output data levels (.8V or 2.0V).
2. TTL/CMOS AC timing measurements are assumed to have an output load of 10pf.
s
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x
0
/
1
C
B
R
0
4
0
6
%
.
1
e
t
o
n
e
e
S
Table 18. Receiver Timing (External Clock Mode)
1. Measurements made from the reference voltage levels of the clock (1.4V) to the valid input or output data levels (.8V or 2.0V).
s
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t
22
DUAL FIBRE CHANNEL DEVICE
S2102
July 14, 1999 / Revision A
Figure 13. Receiver Timing (Full Clock Mode, CMODE = 1)
RBC0x
DOUTx[0:9],
COM_DETx
SERIAL DATA IN
T
3
T
4
RBC1x
RBC0x
DOUTx[0:9],
COM_DETx
SERIAL DATA IN
RBC1x
T
5
T
6
T
7
T
5
T
6
Figure 14. Receiver Timing (Half Clock Mode, CMODE = 0)
Figure 15. Receiver Timing (External Clock Mode) (TBCA to DATA Propagation Delay, TMODE = 0)
DOUTx[0:9],
COM_DETx
SERIAL DATA IN
T
8
TBCA
(Input)
23
S2102
DUAL FIBRE CHANNEL DEVICE
July 14, 1999 / Revision A
Note: Measurements are made at 1.4V level of clocks.
Table 19. S2102 Transmitter (TCLKO Timing)
Figure 16. TCLKO Timing
REFCLK
T
9
TCLKO
s
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C
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L
C
T
%
5
4
%
5
5
%
24
DUAL FIBRE CHANNEL DEVICE
S2102
July 14, 1999 / Revision A
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0
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m
p
p
D
T
2
-
1
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e
m
m
y
S
0
4
0
6
%
.
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%
0
5
t
a
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C
y
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C
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C
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e
m
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K
L
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R
2
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n
.
%
0
8
-
%
0
2
--
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0
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n
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n
e
p
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e
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e
%
7
7
Table 20. Absolute Maximum Ratings
Table 21. Recommended Operating Conditions
Table 22. Reference Clock Requirements
1. Human body model.
25
S2102
DUAL FIBRE CHANNEL DEVICE
July 14, 1999 / Revision A
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2
D
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=
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4
-
=
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2
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3
f
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Table 25. DC Characteristics
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Table 23. Serial Data Timing, Transmit Outputs
Table 24. Serial Data Timing, Receive Inputs
26
DUAL FIBRE CHANNEL DEVICE
S2102
July 14, 1999 / Revision A
OUTPUT LOAD
The S2102 serial outputs do not require output
pulldown resistors.
Figure 20. High Speed Differential Inputs
Figure 17. Serial Input/Output Rise and Fall Time
Figure 21. Receiver Input Eye Diagram Jitter Mask
Figure 18. TTL Input/Output Rise and Fall Time
Figure 19. Serial Output Load
T
r
T
f
80%
20%
50%
80%
20%
50%
T
r
T
f
+2.0V
+0.8V
+2.0V
+0.8V
0.01
f
0.01
f
V
DD
-2.3V
100
0.01
f
0.01
f
V
DD
- 1.3 V
Bit Time
Amplitude
30%
27
S2102
DUAL FIBRE CHANNEL DEVICE
July 14, 1999 / Revision A
Figure 22. Loop Filter Capacitor Connections
CAP1
270
22 nf
CAP2
270
S2102
28
DUAL FIBRE CHANNEL DEVICE
S2102
July 14, 1999 / Revision A
Ordering Information
X
I
F
E
R
P
E
C
I
V
E
D
E
G
A
K
C
A
P
t
i
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c
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i
C
d
e
t
a
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g
e
t
n
I
-
S
2
0
1
2
A
G
B
T
6
5
1
B
T
X
XXXX
X
Prefix Device Package
AMCC is a registered trademark of Applied Micro Circuits Corporation.
Copyright 1999 Applied Micro Circuits Corporation
AMCC reserves the right to make changes to its products or to discontinue any semiconductor product or service without notice, and
advises its customers to obtain the latest version of relevant information to verify, before placing orders, that the information being relied
on is current.
AMCC does not assume any liability arising out of the application or use of any product or circuit described herein, neither does it convey
any license under its patent rights nor the rights of others.
AMCC reserves the right to ship devices of higher grade in place of those of lower grade.
AMCC SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR
USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS.
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