S3014

SONET/SDH CLOCK RECOVERY AND SYNTHESIS UNIT

BiCMOS PECL CLOCK GENERATOR

DEVICE SPECIFICATION

SONET/SDH CLOCK RECOVERY AND SYNTHESIS UNIT

S3014

FEATURES

· Complies with ANSI, Bellcore, and CCITT

specifications for jitter tolerance

· On-chip high frequency PLL with internal loop

filter for clock generation or clock recovery

· Supports clock generation for STS-3/STM-1

(155.52 MHz)

· Supports clock recovery for STS-3/STM-1

(155.52 Mbit/s) or STS-12/STM-4
(622.08 Mbit/s) NRZ data

· Selectable 19.44 MHz, 51.84 MHz, or

155.52 MHz reference frequency

· Lock detect--monitors transition density

and run length

· Low power
· Low-jitter ECL interface
· Small 44 PLCC or CLCC package
· TTL reference clock output

GENERAL DESCRIPTION

The function of the S3014 clock synthesis and recov-
ery unit is to derive high speed timing signals for
SONET/SDH-based equipment. The S3014 is imple-
mented using AMCC's proven Phase Locked Loop
(PLL) technology.

In Clock Recovery mode, the S3014 receives either
an STS-3/STM-1 or STS-12/STM-4 scrambled NRZ
signal and recovers the clock from the data. The chip
outputs a differential ECL bit clock and retimed data.
In Clock Synthesis mode, the S3014 receives a
19.44, 51.84, or 155.52 MHz reference clock and out-
puts an STS-3/STM-1 or STS-12/STM-4 differential
ECL clock.

The S3014 utilizes an on-chip PLL which consists of
a phase detector, a loop filter, and a voltage con-
trolled oscillator (VCO). The phase detector
compares the phase relationship between the VCO
output and the REFCLK input, a loop filter converts
the phase detector output into a smooth DC voltage,
and the DC voltage is input to the VCO whose fre-
quency is varied by this voltage. A block diagram is
shown in Figure 1.

Figure 1. System Block Diagram

REFCKOUT

SERCLKOP/N

LOCKDET

SERDATOP/N

REFCKINP/N

TSTCLKEN

SEL(2:0)

RST

SERDATIP/N

LOOP

FILTER

VCO

CLOCK

DIVIDER

PHASE DETECTOR

LOCK

DETECTOR

CAP1

CAP2

LOS

S3014

SONET/SDH CLOCK RECOVERY AND SYNTHESIS UNIT

S3014 OVERVIEW

Clock Recovery Mode

In the Clock Recovery mode, the S3014 supports
clock recovery for the STS-3/STM-1 and STS-12/
STM-4 rates. In this mode, ECL differential serial data is
input to the chip at the rate specified by the three SEL
pins, and clock recovery is performed on the incoming
data stream. An external ECL differential reference
clock (19.44, 51.84, or 155.52 MHz) is required to
minimize the PLL lock time and provide a stable output
clock source in the absence of serial input data.
Retimed data and clock are output from the S3014.

Clock Synthesis Mode

In the Clock Synthesis mode, the S3014 synthesizes up
to the STS-3/STM-1 and STS-12/STM-4 clock rates
from either a 19.44 MHz, 51.84 MHz, or 155.52 MHz
input reference frequency. STS-3/STM-1 jitter generation
is compliant with the SONET/SDH requirement for
0.01 U.I. (rms) maximum, given 14.1 ps (rms) jitter on
REFCLK in the 12 KHz to 1 MHz frequency band.

In this mode, a crystal oscillator is connected to the
ECL differential reference input and synthesized up to
the output frequency selected using the three SEL
pins. The Clock Synthesis mode is recognized by the
absence of data on the SERDATIP/N input pins. In
this mode, tie the SERDATIP pin to ground and tie the
SERDATIN pin to VTT (-2.0v) or to an ECL low level.
A programmable internal divider outputs a TTL clock
at the same frequency as the reference clock input via
the REFCKOUT output. The lock detect output will
remain consistently low in the Clock Synthesis mode.

CHARACTERISTICS

Performance

The S3014 PLL complies with the minimum jitter toler-
ance for clock recovery proposed for SONET/SDH
equipment defined by the T1X1.6/91-022 document,
when used with differential inputs and outputs as
shown in Figure 2.

Input Jitter Tolerance

Input jitter tolerance is defined as the peak to peak
amplitude of sinusoidal jitter applied on the input sig-
nal that causes an equivalent 1 dB optical/electrical
power penalty. SONET input jitter tolerance require-
ments are shown in Figure 2. The measurement
condition is the input jitter amplitude which causes an
equivalent of 1 dB power penalty.

Jitter Generation

Jitter generation is defined as the amount of jitter at
the OC-N/STS-N output of a SONET equipment.

Jitter generation shall not exceed 0.01 UI rms in OC-3
mode and 0.03 UI rms in OC-12 mode when measured
using a highpass filter with a 12 kHz cutoff frequency.

Serial Data Output Set-up and Hold Time

The output set-up and hold times are represented by
the waveforms shown in Figure 3.

Reference Clock Input

The required characteristics of the reference clock
are outlined below. Unless otherwise noted, specifi-
cations refer to both Clock Recovery and Clock
Synthesis modes of operation. While a single-ended
ECL reference clock may be used, additional jitter
due to edge movement related to threshold variations
from DC offsets may be induced.

Figure 2. Input Jitter Tolerance Specification

0.15

1.5

Sinusoidal

Input Jitter

Amplitude

(UI p-p)

Frequency

OC/STS

Level

(Hz)

(kHz)

(Hz)

300

6.5

250

Figure 3. Clock Output to Data Transition Delay

Output Frequency

155.52 MHz

622.08 MHz

SERDATOP/N Setup Time

2.5 ns

450 ps

SERDATOP/N Hold Time

2.5 ns

650 ps

t su

t h

SERCLKOP/N

SERDATOP/N

S3014

SONET/SDH CLOCK RECOVERY AND SYNTHESIS UNIT

Pin Assignment and Descriptions

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S3014

SONET/SDH CLOCK RECOVERY AND SYNTHESIS UNIT

Pin Assignment and Descriptions (Continued)

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