E4/STM-1/OC-3 ATM INTERFACE CIRCUITS

S3015/S3016

E4/STM-1/OC-3 ATM INTERFACE CIRCUITS

S3015/S3016

FEATURES

· Complies with ANSI, Bellcore, and ITU-T

specifications

· On-chip high-frequency PLL for clock

generation and clock recovery

· On-chip analog circuitry for transformer driver

and equalization

· Supports 139.264 Mbit/s (E4) and 155.52 Mbit/s

(OC-3) transmission rates

· Supports 139.264 Mbit/s and 155.52 Mbit/s

Coded Mark Inversion (CMI) interfaces

· Reference frequencies of 19.44 (OC-3) or

17.408 MHz (E4)

· Interface to both PECL and TTL logic
· Lock detect on clock recovery device
· Low jitter PECL interface
· 1.6W total typ power
· +5V only power supply
· Small 52 PQFP TEP package
· Supports both electrical and optical interfaces

APPLICATIONS

ATM over SONET

OC-3/STM-1 or E4-based transmission systems

OC-3/STM-1 or E4 modules

OC-3/STM-1 or E4 test equipment

Section repeaters

Add drop multiplexors

Broadband cross-connects

· Fiber optic terminators
· Fiber optic test equipment

GENERAL DESCRIPTION

The S3015 transmitter and S3016 receiver derive high
speed timing signals for SONET/SDH or PDHbased
equipment. These circuits are implemented using
AMCC's proven Phase Locked Loop (PLL) technology.
Figures 1a and 1b show typical network applications.

The S3015 and S3016 each have an on-chip VCO
which can be synchronized directly to the incoming data
stream. The chipset can be used with a 19.44 MHz
reference clock when operated in the SONET/SDH OC-
3 mode. In E4 mode the chipset can be operated with a
17.408 MHz reference clock in support of existing
system clocking schemes. On-chip coded-mark-inver-
sion (CMI) encoding and decoding is provided for
139.264 Mbit/s and 155.52 Mbit/s interfaces.

The low jitter PECL interface guarantees compliance
with the bit-error rate requirements of the Bellcore,
ANSI, and ITU-T standards. The S3015/S3016 chipset
is packaged in a .65mm pitch, compact 52-pin PQFP,
offering designers a small package outline.

The S3015 and S3016 provide the major components
on-chip for a coaxial cable interface, including analog
transformer driver circuitry and equalization interface
circuitry.

Figure 1a. Electrical Interface

Figure 1b. Optical Interface

E4/STM-1/OC-3

OVERHEAD

PROCESSOR

OSC

S3016

S3015

XFMR

139/155 Mb/s NRZ

139/155 Mb/s CMI

COAX

139/155 Mb/s NRZ

139/155 Mb/s CMI

17.408/19.44 Mhz

XFMR

COAX

E4/STM-1/OC-3

OVERHEAD

PROCESSOR

OSC

S3016

S3015

155 MHz

155 Mb/s NRZ

OTX

ORX

DEVICE SPECIFICATION

S3015/S3016

E4/STM-1/OC-3 ATM INTERFACE CIRCUITS

SONET/SDH OVERVIEW

Synchronous Optical Network (SONET) is a standard
for connecting one fiber system to another at the optical
level. SONET, together with the Synchronous Digital
Hierarchy (SDH) administered by the ITU-T, form a
single international standard for fiber interconnect be-
tween telephone networks of different countries. SONET
is capable of accommodating a variety of transmission
rates and applications.

The SONET standard is a layered protocol with four
separate layers defined. These are:

· Photonic
· Section
· Line
· Path

Figure 2 shows the layers and their functions. Each of
the layers has overhead bandwidth dedicated to admin-
istration and maintenance. The photonic layer simply

handles the conversion from electrical to optical and
back with no overhead. It is responsible for transmitting
the electrical signals in optical form over the physical
media. The section layer handles the transport of the
framed electrical signals across the optical cable from
one end to the next. Key functions of this layer are
framing, scrambling, and error monitoring. The line
layer is responsible for the reliable transmission of the
path layer information stream carrying voice, data, and
video signals. Its main functions are synchronization,
multiplexing, and reliable transport. The path layer is
responsible for the actual transport of services at the
appropriate signaling rates.

Data Rates and Signal Hierarchy

Table 1 contains the data rates and signal designations
of the SONET hierarchy. The lowest level is the basic
SONET signal referred to as the synchronous transport
signal level-1 (STS-1). An STS-

N signal is made up of

N byte-interleaved STS-1 signals. The optical counter-
part of each STS-

N signal is an optical carrier level-N

signal (OC-

N). The S3015/S3016 chipset supports OC-

3 rates (155.52 Mbit/s).

Frame and Byte Boundary Detection

The SONET/SDH fundamental frame format for STS-3
consists of nine transport overhead bytes followed by
Synchronous Payload Envelope (SPE) bytes. This pat-
tern of 9 overhead and 261 SPE bytes is repeated
nine times in each frame. Frame and byte boundaries
are detected using the A1 and A2 bytes found in the
transport overhead. (See Figure 3.)

For more details on SONET operations, refer to the
ANSI SONET standard document.

Elec.

ITU-T

Optical Data Rate (Mbit/s)

STS-1

OC-1

51.84

STS-3

STM-1

OC-3

155.52

STS-12

STM-4

OC-12

622.08

STS-24

OC-24

1244.16

STS-48

STM-16

OC-48

2488.32

Table 1. SONET Signal Hierarchy

Figure 3. SONET Structure

End Equipment

Payload to

SPE mapping

Maintenance,

protection,

switching

Optical

transmission

Scrambling,

framing

Fiber Cable

End Equipment

Section layer

Photonic layer

Line layer

Path layer

Section layer

Photonic layer

Line layer

Functions

Transport Overhead

9 Columns

Synchronous

Payload

Envelope

125

sec

9 x 261 =

2349 bytes

Rows

Figure 3. STS-3 Frame Format

E4/STM-1/OC-3 ATM INTERFACE CIRCUITS

S3015/S3016

S3015 TRANSMITTER
FUNCTIONAL DESCRIPTION

The S3015 transmitter chip performs the last stage of
digital processing of a transmit SONET STS-3 or ITU-
T E4 bit serial data stream. A Coded Mark Inversion
(CMI) encoder can be enabled for encoding STS-3
electrical and E4 signals.

Clock Recovery

If serial data is present on the SERDATIP/N inputs, the
clock is recovered from the serial data stream at 139.264
MHz or 155.52 MHz and synthesized to 278.528 MHz
or 311.04 MHz to CMI encode the incoming data.

Optical and Electrical Interfaces

The digital data outputs (SERDATOP/N) are the PECL
outputs for an optical interface and are to be connected
to an electrical to optical converter, as shown in Figure
18. This data is also routed to two on-chip transformer
drivers and sent out on XFRMDRVA and XFRMDRVB
to drive the transformers of the electrical interface, as
shown in Figure 20. These outputs are shut off when the
reset is active, XFRMEN is active, or when the chip is
in NRZ mode and the data inputs are in the logic zero
state. The electrical characteristics for the transformer
drivers are shown in Table 5.

S3015/S3016 OVERVIEW

The S3015 transmitter and the S3016 receiver can be
used to implement the front end of STS-3, OC-3 or E4
equipment. The block diagrams in Figures 4 and 10
show the basic operation of both chips.

When serial data is present at the input of the transmitter,
the S3015 VCO synchronizes directly to the incoming data,
which is retimed for the purpose of optional CMI encod-
ing. In the absence of incoming serial data, the S3015
operates as a clock synthesizer. In this mode, a crystal
oscillator is connected to the TTL reference input and
synthesized up to the 155 MHz output frequency. The
S3016 receiver performs clock recovery by synchroniz-
ing its on-chip VCO directly to the incoming data stream.

The S3015 provides a PECL output for an optical
interface and two transformer driver outputs for an
electrical interface. One of these drivers is a monitor
output. The S3016 provides a PECL input for an optical
interface and an analog input for an electrical interface.

When the chipset is used in an electrical interface, the
PECL output of the transmitter can be connected to the
PECL input of the receiver to implement a diagnostic
loopback mode for test. When the chipset is used in an
optical interface, a transformer driver output of the
transmitter can be connected to the analog input of the
receiver to implement the loopback mode.

Figure 4. S3015 OC3/STM-1/E4 Transmitter Functional Block Diagram

SERCLKOP/N

REFCKOUT

SERDATOP/N

XFRMEN

SERDATEN

XFRMDRVB

XFRMDRVA

TRANSFORMER
DRIVERS

REFCKIN

TSTCLKEN

CMISEL

DLCV

RSTB

SERDATIP/N

LOOP

FILTER

VCO

CLOCK

DIVIDER

PHASE DETECTOR

CAP1

CAP2

C
M

S3015/S3016

E4/STM-1/OC-3 ATM INTERFACE CIRCUITS

CMI Encoding

Coded Mark Inversion format (CMI) ensures at least
one data transition per 1.5 bit periods, thus aiding
the clock recovery process. Zeros are represented
by a Low state for one half a bit period, followed by
a High state for the rest of that bit period. Ones are
represented by a steady Low or High state for a full
bit period. The state of the ones bit period alternates
at each occurrence of a one. Figure 5 shows an
example of CMI-encoded data. The STS-3 electrical
interface and the E4 interface are specified to have
CMI-encoded data.

The CMI encoder on the S3015 accepts serial data
from SERDATIP/N at 139.264 or 155.52 Mb/s. The
data is then encoded into CMI format, and the result
is shifted out with transitions at twice the basic data
rate. The CMISEL input controls whether the CMI en-
coder is in the data path. A CMI code violation can be
inserted for diagnostic purposes by activating the
DLCV input. The DLCV input is sampled on every
cycle of the serial clock to allow a single or multiple
line code violations to be inserted. This violation is
either an inverted zero code or an inversion of the
alternating ones logic level, depending on the state of
the data. Subsequent one codes take into account
the induced violation to avoid error multiplication.

Jitter Generation

Jitter Generation is defined as the amount of jitter at the
OC-3 or E-4 output of equipment. Jitter generation for
OC-3 shall not exceed 0.01 UI rms when measured
using a highpass filter with a 12 kHz cutoff frequency.

For STM-1 and E4, the jitter generated shall not exceed
the specifications shown in Figure 6.

In order to meet the SONET, STM-1 E4 jitter specifica-
tions as shown in Figure 6, the SERDATIP/N serial data
input must meet the jitter characteristics as shown in
Figure 7.

Figure 6. Jitter Generation Specifications

Compliant to G.823 and G.825

Figure 7. S3015 Maximum Allowable Input Jitter

STM-1

500

f1(Hz)

1. UI rms
2. UI pp

200

f2(KHz)

1.3

f3(MHz)

3.5

1.5

(2)

1.5

(2)

.15

(2)

OC-3

.01

(1)

.01

(1)

.075

(2)

500Hz

STM-1

f2(KHz)

1. UI rms
2. UI pp

1.45

(2)

1.45

(2)

.10

(2)

OC-3

.005

(1)

.005

(1)

.025

(2)

1.3 MHz

225 KHz

Slope = +20 dB/decade

Figure 5. CMI Encoded Data

S3015/S3016

E4/STM-1/OC-3 ATM INTERFACE CIRCUITS

S3016 RECEIVER FUNCTIONAL
DESCRIPTION

The S3016 receiver provides the first stage of digital
processing of a receive SONET STS-3 or ITU-T E4 serial
bit stream. A Coded Mark Inversion (CMI) decoder can
be enabled for decoding STS-3 electrical and E4 signals.

Clock recovery is performed on the incoming
scrambled NRZ or CMIcoded data stream. A reference
clock is required for phase locked loop start-up and
proper operation under loss of signal conditions. An
integral prescaler and phase locked loop circuit is used
to multiply this reference frequency to the nominal bit rate.

Clock Recovery

The Clock Recovery function, as shown in the block
diagram in Figure 10, generates a clock that is fre-
quency matched to the incoming data baud rate at
the SERDATIP/N differential inputs. The clock is
phase aligned by a PLL so that it samples the data
in the center of the data eye pattern.

The phase relationship between the edge transitions
of the data and those of the generated clock are
compared by a phase/frequency discriminator. Output
pulses from the discriminator indicate the required
direction of phase corrections. These pulses are
smoothed by an integral loop filter. The output of the
loop filter controls the frequency of the Voltage Con-

trolled Oscillator (VCO), which generates the recov-
ered clock. Frequency stability without incoming data
is guaranteed by an alternate reference input
(REFCKIN) to which the PLL locks when data is lost.

When the test clock enable (TSTCLKEN) input is set
high, the clock recovery block is disabled. The refer-
ence clock (REFCKIN) is used as the bit rate clock
input in place of the recovered clock. This feature is
used for functional testing of the device.

The loop filter transfer function is optimized to enable
the PLL to track the jitter, yet tolerate the minimum
transition density expected in a received SONET or
E4 data signal. This transfer function yields a typical
capture time of 16

s for random incoming NRZ data.

The total loop dynamics of the clock recovery PLL yield
a jitter tolerance which exceeds the minimum tolerance
proposed for OC-3/STM-1/E4 equipment by the Bellcore
and ITU-T documents, shown in Figure 13.

Optical and Electrical Interfaces

The digital data inputs (SERDATIP/N) are the PECL
inputs from an optical to electrical converter, as shown
in Figure 16. The data input for the coaxial interface is
ANDATIN, which is the serial data input from the equal-
izer circuit and should be connected as shown in Figure
17. The EQUALSEL input is used to select either
SERDATIP/N or ANDATIN.

SERCLKOP/N

REFCKOUT

LCV

LOSOUT

SERDATOP/N

REFCKIN

TSTCLKEN

CMISEL

RSTB

EQUALSEL

LOSIN

LOSREF

LOSOPT

ANDATIN

SERDATIP/N

LOOP

FILTER

VCO

CLOCK

DIVIDER

PHASE DETECTOR

LOCK

DETECTOR

CAP1

CAP2

BUFINA, BUFINB

BUFOUT

2:1

MUX

2:1

MUX

Figure 10. S3016 OC-3/STM-1/E4 Receiver Functional Block Diagram

E4/STM-1/OC-3 ATM INTERFACE CIRCUITS

S3015/S3016

CMI Decoding

The CMI decoder block on the S3016 accepts serial
data from the SERDATIP/N input at the rate of 139.264
or 155.52 Mb/s. The incoming CMI data, which has
transitions that represent this data rate (the clock asso-
ciated with this data would be running at twice this rate),
is then decoded from CMI to NRZ format.

Loss of Signal

The clock recovery circuit monitors the incoming data
stream for loss of signal. If the incoming encoded data
stream has had no transitions continuously for 96 to 224
recovered clock cycles, loss of signal is declared and
the PLL will switch from locking onto the incoming data
to locking onto the reference clock per the requirements
of G.775. Alternatively, the loss-of signal (LOSIN) input
can force a loss-of-signal condition. This signal is com-
pared internally against the LOSREF input reference
voltage. This input can be set to meet the conditions
shown in Figure 11. If the zero to peak signal level drops
below the LOSREF/20 voltage level for more than 96 to
224 bit intervals, a loss of signal condition will be
indicated on the LOSOUT pin and the PLL will change
its reference from the serial data stream to the reference
clock. When the peak input voltage is greater than
LOSREF/10, the loss of signal condition will be
deasserted and the PLL will recover the clock from the
serial data inputs.

In NRZ mode, a logic low level on the LOSOPT input will
cause the PLL to change its reference to the reference
clock. This pin should be driven by a PECL compatible
level signal detect signal from the fiber optic receiver.

Serial Clock Output to Data Output Timing

The serial data is clocked out on the falling edge of
SERCLKOP. (See Figure 12.) This timing is valid in
both NRZ and CMI modes.

Input Jitter Tolerance

Input jitter tolerance is defined as the peak to peak
amplitude of sinusoidal jitter applied on the input signal
that causes an equivalent 1 dB optical/electrical power
penalty. OC-3 and E-4 input jitter tolerance require-
ments are shown in Figure 13.

The S3016 PLL complies with the minimum jitter toler-
ance for clock recovery proposed for SONET/SDH
equipment defined by the Bellcore TA-NWT-000253
standard when used as shown in Figure 13. The S3016
PLL also complies with the minimum jitter tolerance for
clock recovery as defined in the ITU-T E4 specification
when used as shown in Figure 17.

OC-3

(Hz)

TBD

(Hz)

TBD

300

(Hz)

200

6.5

(KHz)

0.5

(KHz)

(MHz)

1.3

1.5

.15

STM-1 (Optical) 0.125 19.3

500

6.5

1.3

1.5 0.15

STM-1 (Electrical) 0.125 19.3

500

3.25

1.3

1.5 0.075

0.075

Sinusoidal
Input Jitter

Amplitude

(UI p-p)

Figure 13. Clock Recovery Jitter Tolerance
Compliant to G.823 and G.825

maximum

cable loss

nominal value

Tolerance range

"no transition condition" or "transition

condition" may be declared

"transition condition"

must be declared

"no transition condition"

must be declared

Level below Nominal

The signal level 17 is (maximum cable loss +3)
dB below nominal.

3 dB

The signal level 35 is greater than the maximum
expected cross-talk level.

Figure 11. Criteria for determination of transition
conditions. Compliant to G.775.

Note:
1. Only tested to 20 due to test equipment limitation.

SERCLKOP

SERDATOP/N

tPSER

Figure 12. S3016 Clock to Data Timing

S3015/S3016

E4/STM-1/OC-3 ATM INTERFACE CIRCUITS

Figure 14. Loopback Diagram

S3015

S3016

S3015

S3016

Control

CLK

Diagnostic

Loopback

Diagnostic

Loopback

CLK

Control

Reference Clock Input

The reference clock input seen in Figure 10 provides
backup reference clock signals to the clock recovery
block when the clock recovery block detects a loss of
signal condition. It contains a counter that divides the
clock output from the clock recovery block down to the
same frequency as the reference clock REFCKIN.

OTHER OPERATING MODES

Diagnostic Loopback

When the chipset is used in an electrical interface, the
serial data output (SERDATOP/N) of the transmitter
can be connected the serial data input (SERDATIP/N)
of the receiver to implement a loopback test for diagnos-
tic purposes, as shown in Figure 14. In this mode,
SERDATEN on the transmitter and EQUALSEL on the
receiver are both held low. LOSOPT on the receiver is
held high or not connected.

Test Mode

The Test Clock Enable (TSTCLKEN) inputs on both
chips provide access to the PLL.

The PLL-generated clock source on both the S3015
and S3016 can be bypassed by setting TSTCLKEN
high. In this mode, an externally generated clock source
must be applied at the REFCLKIN input.

Clock Synthesis

In the Clock Synthesis mode, the S3015 synthesizes
the E4 (139.264 MHz) clock from a 17.408 MHz crystal
oscillator or the STS-3/STM-1 (155.52 MHz) clock from
a 19.44 MHz crystal oscillator. In this mode, a crystal
oscillator is connected to the TTL reference input and
synthesized up to the output frequency.

The S3015 PLL complies with jitter generation for clock
synthesis proposed for SONET/SDH equipment de-
fined by the Bellcore TA-NWT-000253 standard, when
used with a crystal reference source as defined in Table 4.

E4/STM-1/OC-3 ATM INTERFACE CIRCUITS

S3015/S3016

S3015 Pin Assignment and Descriptions

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E4/STM-1/OC-3 ATM INTERFACE CIRCUITS

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E4/STM-1/OC-3 ATM INTERFACE CIRCUITS

S3015/S3016

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E4/STM-1/OC-3 ATM INTERFACE CIRCUITS

Table 2. S3015/S3016 Clock Recovery Mode Performance Specifications

Parameter

Min

Typ

Max

Units

Condition

Nominal VCO
Center Frequency

622.08

MHz

Given REFCKIN = VCO

OC3/STS3

Lock Range

+8, -12

With respect to fixed reference

frequency

Acquisition Lock Time

sec

With device already powered up
and valid REFCLK

Reference Clock
Input Duty Cycle

% of UI

Reference Clock Rise &
Fall Times

5.0

10% to 90% of amplitude

PECL Output Rise & Fall
Times

850

10% to 90%, 50

load,

5 pf cap

Reference Clock
Frequency Tolerance

-100

100

ppm

SERCLKOP Falling to
SERDATO Valid Prop
Delay

100

500

See Figure 13

Table 4. Electrical Characteristics for Transformer Driver

= +5V, T

= +25

C, input AC coupled unless otherwise noted.)

Parameter

Min

Typ

Max

Units

Condition

Operating Frequency

155

MHz

270

|| 3pF load

VSWR

1.3:1

1.5:1

A.C. Coupled Termination

1. For output waveform characteristics, see Figures 8 and 9.
2. Up to 250 MHz.

(2)

Parameter

Min

Typ

Max

Units

Condition

PECL Data Output Jitter
(S3015 SERDATOP/N)
OC3/STS3

E4STS3 CMI

ps (rms)

In CSU mode, given

· 56 ps rms jitter on
REFCKIN in 12KHz to
1 MHz band
· 28 ps rms jitter on
REFCKIN in 12KHz to
1 MHz band

Reference Clock
Frequency Tolerance
Clock Synthesis

-20

+20

ppm

Required to meet SONET output
jitter generation specification

Table 3. S3015 Clock Synthesis Mode Performance Specifications

1. Specification based on design values. Not tested.

SER

(1)

E4/STM-1/OC-3 ATM INTERFACE CIRCUITS

S3015/S3016

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

Peak to Peak Input Voltage Range

1.3

Common-Mode Rejection Ratio

Power-Supply Rejection Ratio

Input Sensitivity

110

DC offset at input

Table 5. Electrical Characteristics for ANDATIN Input

= +5V, T

= +25

C, input AC coupled unless otherwise noted.)

1. Up to 300 KHz
2. Signal is undefined if left floating

iptp

CMRR

(1)

PSRR

(1)

= MIN to MAX

(2)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

Peak to Peak Input Voltage Range

1.1

Common-Mode Rejection Ratio

Power-Supply Rejection Ratio

Signal Level for LOS detected

LOS-

REF/30

LOS-

REF/20

LOS-

REF/10

V/V

Signal Level for LOS cleared

LOS-

REF/15

LOS-

REF/10

LOS-

REF/5

V/V

Hysterisis between "trans. cond."
and "no trans. cond."

Table 6. Electrical Characteristics for LOSIN Input

= +5V, T

= +25

C, input AC coupled unless otherwise noted.)

(2)

iptp

CMRR

(1)

PSRR

(1)

= MIN to MAX

1. Up to 300 KHz
2. LOSREF >0.5 volts
3. LOS detected and LOS cleared will maintain 2:1 ratio

5%.

Voltage Applied at

LOSREF

Compare Voltage #1

Compare Voltage #2

Hysterisis

1.4 Volts
0.7 Volts
0.3 Volts

140 mV

0.6dB

70 mV

1dB

30 mV

1.6dB

70 mV

1dB

35 mV

1.6dB

15 mV

3.5dB

6dB +1.6 -1.4dB
6dB +2.7 -2.0dB
6dB +6.0 -3.7dB

Below are typical operating conditions:

(3)

E4/STM-1/OC-3 ATM INTERFACE CIRCUITS

S3015/S3016

VOL

VOH

VIK

IIH
II

IIL

IOS

Output LOW Voltage

Output HIGH Voltage

Input Clamp Diode Voltage

VCC = MIN, IOL = 8 ma
VCC = MIN, IOH = -1 ma

VCC = MIN, IIN = -18 ma

VCC = MAX, VIN = 2.7V
VCC = MAX, VIN = 5.5V

VCC = MAX, VIN = 0.5V

VCC = MAX, VOUT = 0.5V

2.7

-1.2

-100.0

-400.0

Volts

0.5

1.0

50.0

-25.0

Input HIGH Current

Input HIGH current at
Max. VCC

Input LOW Current

Output Short Circuit Current

Symbol

VIL1
VIH1

Input LOW Voltage

Input HIGH Voltage

Guaranteed Input LOW Voltage

Guaranteed Input HIGH Voltage

2.0

0.8

Volts

Parameter

Min

Typ

Max

Unit

Conditions

These input levels provide zero noise immunity and should only be tested in a static, noise-free environment.

TTL Input/Output DC Characteristics

= -40

C to +85

C, V

= 5 V

5%)

Symbol

VIL

VIH

VIL

VIH

VOL

VOH
VOD

VID
IIH
IIL

Input LOW Voltage

Input HIGH Voltage

Input LOW Voltage

Input HIGH Voltage

Output LOW Voltage

Output HIGH Voltage

Guaranteed Input LOW Voltage
for single-ended inputs

Guaranteed Input HIGH Voltage
for single-ended inputs

Guaranteed Input LOW Voltage
for differential inputs

Guaranteed Input HIGH Voltage
for differential inputs

50 ohm termination to VCC -2V

50 ohm termination to VCC -2V
Differential Output Voltage

Differential Input Voltage

VID = 500mV
VID = 500mV

-0.500

0.390

0.250

0.500

VCC -2.000

VCC -1.225

VCC -1.441

VCC -0.570

VCC -2.000

VCC -0.700

VCC -1.750

VCC -0.450

VCC -2.000

VCC -1.500

VCC -1.110

VCC -0.670

Volts

20.000

1.400

1.330

Output Diff. Voltage

Input Diff. Voltage

Input High Current

Input Low Current

Parameter

Min

Typ

Max

Unit

Conditions

PECL Input/Output DC Characteristics

= -40

C to +85

C, V

= 5 V

5%)

These conditions will be met with no airflow.

When not used, tie the positive differential PECL pin to VCC and the negative
differential ECL pin to ground via a 3.9K resistor.

S3015/S3016

E4/STM-1/OC-3 ATM INTERFACE CIRCUITS

GRADE

TRANSMITTER

3015

S Industrial/

commercial

A 52 TQFP TEP

w/DW0045-29 heatsink unattached

Ordering Information

GRADE

3016

RECEIVER

S Industrial/

commercial

X XXXX X / XX

Grade Part number Package H0 for no heatsink (identifier not marked on part)

A 52 TQFP TEP

w/DW0045-29 heatsink unattached

H0 No Heatsink

Processor Interface

PMC PM5345

SUNI

Saturn User Network Interface

PMC PM5346

SUNI-Lite

Saturn User Network Interface

PMC PM5347

SUNI-Plus

Saturn User Network Interface

IGT WAC-013-A

SONET LAN ATM Processor

TRANSWITCH SYN155

155 Mbit/s Synchronizer

TI SABRE TDC 1500

155 Mbit/s Processor

AMCC S3011/12

SONET/SDH/ATM 0C3 Transmitter & Receiver

Electrical Interface

Mini-Circuits

MCL TXI-R5

Wideband RF Transformer (Surface Mount)

Mini-Circuits

MCL TO-75

Wideband RF Transformer (Through-Hole)

Optical Interface

HP HFBR-520x

155 Mbit/s

Fiber Optic Transceiver

CTS ODL-1408X

155 Mbit/s

Fiber Optic Transceiver

Sumitomo SDM4123-XC

155 Mbit/s

Fiber Optic Transceiver

AMP 269039-1

155 Mbit/s

Fiber Optic Transceiver

Table 8. Suggested Interface Devices

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: S3015

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: S3015