1
S3029
SONET/SDH/ATM 155 MBIT/S QUAD TRANSCEIVER
February 19, 1999 / Revision B
BiCMOS PECL CLOCK GENERATOR
DEVICE
SPECIFICATION
SONET/SDH/ATM 155 MBIT/S QUAD TRANSCEIVER
S3029
FEATURES
Complies with ANSI, Bellcore, and ITU-T
specifications for jitter tolerance, jitter generation
Five on-chip high frequency PLLs with
internal loop filters for clock recovery
Supports clock recovery for STS-3/STM-1
(155.52 Mbit/s) NRZ data
Clock Multiplier PLL for transmit clock
generation
19.44 or 51.84 MHz reference frequency
Lock detect--monitors run length and
frequency
Low-jitter differential interface
3.3V supply
Available in a 64-pin TQFP package
Compatible with IgT WAC-413 ATM Quad-
UNI processor
GENERAL DESCRIPTION
The function of the S3029 clock synthesis and recov-
ery unit is to derive high speed timing signals for
SONET/SDH-based equipment. The S3029 is imple-
mented using AMCC's proven Phase Locked Loop
(PLL) technology.
The S3029 receives four STS-3/STM-1 scrambled NRZ
signals and recovers the clock from the data and
generates a 155 MHz transmit clock. The chip out-
puts a differential PECL bit clock and retimed data.
Figure 1 shows a typical network application.
The S3029 utilizes five on-chip PLLs which consist of
a phase detector, a loop filter, and a voltage con-
trolled oscillator (VCO). The phase detector
compares the phase relationship between the VCO
output and the serial data input. A loop filter converts
the phase detector output into a smooth DC voltage,
and the DC voltage is input to the VCO whose fre-
quency is varied by this voltage. A block diagram is
shown in Figure 2. There is a single clock multiplier
PLL which generates a 155 MHz transmit clock from
a 19.44 or 51.84 MHz input.
Figure 1. System Block Diagram
155 Mbp/s
Network
Interface Processor
155 Mbp/s
Network
Interface Processor
155 Mbp/s
Network
Interface Processor
155 Mbp/s
Network
Interface Processor
TXCLK
TXDATA
RXDATA
RXCLK
Optical
Transceiver
Optical
Transceiver
S3029
S3029
Optical
Transceiver
Optical
Transceiver
RX
RX
RX
RX
TXCLK
TXDATA
RXDATA
RXCLK
TXCLK
TXDATA
RXDATA
RXCLK
TXCLK
TXDATA
RXDATA
RXCLK
155 Mbp/s
Network
Interface Processor
155 Mbp/s
Network
Interface Processor
155 Mbp/s
Network
Interface Processor
155 Mbp/s
Network
Interface Processor
TXCLK
TXDATA
RXDATA
RXCLK
Optical
Transceiver
Optical
Transceiver
Optical
Transceiver
Optical
Transceiver
RX
RX
RX
RX
TXCLK
TXDATA
RXDATA
RXCLK
TXCLK
TXDATA
RXDATA
RXCLK
TXCLK
TXDATA
RXDATA
RXCLK
2
S3029
SONET/SDH/ATM 155 MBIT/S QUAD TRANSCEIVER
February 19, 1999 / Revision B
Figure 2. Functional Block Diagram
PLL CLOCK
RECOVERY
PLL CLOCK
MULTIPLIER
D
BITCLK
Q
QN
SERDATIP0
REFCLK
LCKREFN0
155 MHz CLK
SERDATIN0
REFCKINP
REFCKINN
SERDATIP1
SERDATIN1
SERDATIP2
SERDATIN2
SERDATIP3
SERDATIN3
LOCKDET0
SERCLKOP0
SERCLKON0
TXCLKOP
TXCLKON
PLL CLOCK
RECOVERY
D
BITCLK
Q
QN
REFCLK
LCKREFN1
LOCKDET1
SERCLKOP1
SERCLKON1
PLL CLOCK
RECOVERY
D
BITCLK
Q
QN
REFCLK
LCKREFN2
LOCKDET2
SERCLKOP2
SERCLKON2
PLL CLOCK
RECOVERY
D
BITCLK
Q
QN
REFCLK
LCKREFN3
SD3
SD2
SD1
SD0
TSTCLKEN
REFSEL
LOCKDET3
SERDATOP3
SERCLKOP3
SERCLKON3
SERDATON3
SERDATOP1
SERDATON1
SERDATOP0
SERDATON0
SERDATOP2
SERDATON2
3
S3029
SONET/SDH/ATM 155 MBIT/S QUAD TRANSCEIVER
February 19, 1999 / Revision B
S3029 OVERVIEW
The S3029 supports clock recovery for the STS-3/
STM-1 data rate. The LVPECL differential serial data
is input to the chip and clock recovery is performed on
the incoming data stream. An external reference clock
is required to minimize the PLL lock time and provide
a stable output clock source in the absence of serial
input data. Retimed data and clock are output from the
S3029.
CHARACTERISTICS
Performance
The S3029 PLL complies with the minimum jitter tol-
erance for clock recovery proposed for SONET/SDH
equipment defined by the T1X1.6/91-022 document,
when used with differential inputs and outputs as
shown in Figure 3.
Input Jitter Tolerance
Input jitter tolerance is defined as the peak to peak
amplitude of sinusoidal jitter applied on the input sig-
nal that causes an equivalent 1 dB optical/electrical
power penalty. SONET input jitter tolerance require-
ments are shown in Figure 3. The measurement
condition is the input jitter amplitude which causes an
equivalent of 1 dB power penalty.
Serial Data Output Set-up and Hold Time
The output set-up and hold times are represented by
the waveforms shown in Figure 4.
Figure 4. Clock Output to Data Transition Delay
Output Frequency
155.52 MHz
SERDATOP/N Setup Time
2.5 ns
SERDATOP/N Hold Time
2.5 ns
t su
t h
SERCLKOP/N
SERDATOP/N
Figure 3. Input Jitter Tolerance Specification
f0
f1
f2
f3
ft
0.15
1.5
15
Sinusodal
Input Jitter
Amplitude
(UI p-p)
Frequency
OC/STS
Level
f0
(Hz)
f2
(Hz)
f3
(kHz)
ft
(kHz)
f1
(Hz)
3
10
30
300
6.5
75
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Table 1.
4
S3029
SONET/SDH/ATM 155 MBIT/S QUAD TRANSCEIVER
February 19, 1999 / Revision B
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S3029 Transceiver Pin Assignment and Descriptions
5
S3029
SONET/SDH/ATM 155 MBIT/S QUAD TRANSCEIVER
February 19, 1999 / Revision B
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S3029 Transceiver Pin Assignment and Descriptions (continued)
6
S3029
SONET/SDH/ATM 155 MBIT/S QUAD TRANSCEIVER
February 19, 1999 / Revision B
Figure 5. S3029 64 TQFP Package
7
S3029
SONET/SDH/ATM 155 MBIT/S QUAD TRANSCEIVER
February 19, 1999 / Revision B
Figure 6. S3029 64 TQFP Pinout
1
2
3
4
5
6
7
8
9
10
11
19
20
21
22
23
24
25
26
27
28
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61
60
59
58
57
56
55
54
53
52
48
47
46
45
44
43
42
41
40
39
38
S3029
37
36
TXoPOW
TXoGRD
SERCLKOP0
SERCLKON0
SERDATOP0
SERDATON0
CRUoPOW0
CRUoGRD0
SERDATOP1
SERDATON1
SERCLKOP1
SERCLKON1
CRUoPOW1
35
34
33
CRUoGRD1
CRUoPOW2
CRUoGRD2
17
18
ACRUGRD3
LOCKDET3
SERDATIN3
SERDATIP3
SERCLKON3
SERCLKoP3
SERDATON3
SERDATOP3
CRUoGRD3
CRUoPOW3
SERDATON2
LOCKDET2
ACRUPOW3
30
31
32
SERDATOP2
SERCLKON2
SERCLKOP2
64
63
OPAVCC
OPAGRD
LCKREFN2
LCKREFN3
VCOVCC
VCOGRD
SD0
SD1
REFCKINN
REFCKINP
SD2
LCKREFN0
LCKREFN1
51
50
49
SD3
TXCLKOP
TXCLKON
12
13
SERDATIP0
SERDATIN0
TSTCLKEN
ACRUPOW0
ACRUGRD0
REFSEL
SERDATIP1
SERDATIN1
LOCKDET0
ACRUPOW1
ACRUGRD1
ACRUPOW2
ACRUGRD2
14
15
16
LOCKDET1
SERDATIP2
SERDATIN2
TOP VIEW
8
S3029
SONET/SDH/ATM 155 MBIT/S QUAD TRANSCEIVER
February 19, 1999 / Revision B
Performance Specifications
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1 Guaranteed but not tested.
9
S3029
SONET/SDH/ATM 155 MBIT/S QUAD TRANSCEIVER
February 19, 1999 / Revision B
Recommended Operating Conditions
Absolute Maximum Ratings
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10
S3029
SONET/SDH/ATM 155 MBIT/S QUAD TRANSCEIVER
February 19, 1999 / Revision B
TTL Input/Output DC Characteristics
1
1. These conditions will be met with no airflow.
2. When not used, tie the positive differential PECL pin to V
CC
and the negative differential PECL pin to ground via a 3.9K resistor.
(T
A
= -40
C to +85
C, V
CC
= 3.3 V
5%)
PECL Output Loading
Recommended Termination of Differential
PECL Signals
PECL Input/Output DC Characteristics
1,2
(T
A
= -40
C to +85
C, V
CC
= 3.3V
5%)
2. These input levels provide a zeronoise immunity and should only be tested in a static, noise-free environment.
Symbol
Parameter
Test Conditions
Min
Max
Unit
VIL
2
VIH
2
IIL
IIH
II
IOS
VIK
VOL
VOH
Input LOW Voltage
Input HIGH Voltage
Input LOW Current
Input HIGH Current
Input HIGH Current at Max VCC
Output Short Circuit Current
Input Clamp Diode Voltage
TTL Output LOW Voltage
TTL Output HIGH Voltage
Guaranteed Input LOW Voltage for all inputs
VCC = MAX, VIN = 0.5V
VCC = MAX, VIN = 2.7V
VCC = MAX, VIN = 3.5V
VCC = MAX, VOUT = 0.5V
VCC = MIN, IIN = -18.0mA
VCC = MIN, IOL = 2mA
VCC = MIN, IOH = -.10mA
2.0
-400.0
-50.0
2.2
0.8
50.0
1.0
-5.0
0.5
Volts
Volts
uA
uA
mA
mA
Volts
Volts
-1.2
Volts
Guaranteed Input HIGH Voltage for all inputs
Symbol
VIL
VIH
VIL
VIH
VOL
VOH
VOD
VID
IIHD
IILD
Input LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input HIGH Voltage
Output LOW Voltage
Output HIGH Voltage
Guaranteed Input LOW Voltage
for single-ended inputs
Guaranteed Input HIGH Voltage
for single-ended inputs
Guaranteed Input LOW Voltage
for differential inputs
Guaranteed Input HIGH Voltage
for differential inputs
400 ohm termination to GND
400 ohm termination to GND
Differential Output Voltage
Differential Input Voltage
VID = 500mV
VID = 500mV
-0.500
-0.500
0.390
0.200
0.500
VCC -2.000
VCC -1.225
VCC -1.441
VCC -0.570
VCC -2.000
VCC -0.700
VCC -1.750
VCC -0.450
VCC -2.000
VCC -1.300
VCC -1.110
VCC -0.670
Volts
Volts
Volts
Volts
Volts
Volts
Volts
Volts
A
A
20.000
20.000
4
4
1.400
1.000
Output Diff. Voltage
Input Diff. Voltage
Diff. Input High Current
Diff. Input Low Current
IIH
SD Inputs have internal 1K to GND
load resistor.
SD Inputs have internal 1K to GND
load resistor.
mA
Single-ended input High Current
IIL
mA
Single-ended input LOW Current
Parameter
Min
Typ
Max
Unit
Conditions
400
400
100
400
11
S3029
SONET/SDH/ATM 155 MBIT/S QUAD TRANSCEIVER
February 19, 1999 / Revision B
X XXXX XX
Prefix Device Package
Ordering Information
AMCC is a registered trademark of Applied Micro Circuits Corporation.
Copyright 1999 Applied Micro Circuits Corporation
AMCC reserves the right to make changes to its products or to discontinue any semiconductor product or service without notice, and
advises its customers to obtain the latest version of relevant information to verify, before placing orders, that the information being relied
on is current.
AMCC does not assume any liability arising out of the application or use of any product or circuit described herein, neither does it convey
any license under its patent rights nor the rights of others.
AMCC reserves the right to ship devices of higher grade in place of those of lower grade.
AMCC SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR
USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS.
Applied Micro Circuits Corporation 6290 Sequence Dr., San Diego, CA 92121
Phone: (619) 450-9333 (800) 755-2622 Fax: (619) 450-9885
http://www.amcc.com
C
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