E4/STM-1/OC-3 ATM TRANSCEIVER
S3031B
1
August 19, 1999 / Revision D
E4/STM-1/OC-3 ATM TRANSCEIVER
S3031B
FEATURES
Complies with Bellcore and ITU-T
specifications
On-chip high-frequency PLLs for clock
generation and clock recovery
On-chip analog circuitry for transformer
driver and equalization
Supports 139.264 Mbps (E4) and 155.52
Mbps (OC-3) transmission rates
Supports 139.264 Mbps and 155.52 Mbps
Coded Mark Inversion (CMI) interfaces
TTL Reference frequencies of 19.44 and
38.88 MHz (OC-3) or 17.408 and 34.816
MHz (E4)
Interface to both PECL and TTL logic
Lock detect on clock recovery function --
monitors run length and frequency
Serial and 4 bit (nibble) system interfaces
Low jitter PECL interface
+5V operation
100 PQFP/TEP package
Supports both electrical and optical interfaces
APPLICATIONS
ATM over SONET/SDH
OC-3/STM-1 or E4-based transmission
systems
OC-3/STM-1 or E4 modules
OC-3/STM-1 or E4 test equipment
Section repeaters
Add Drop Multiplexers (ADM)
Broadband cross-connects
Fiber optic terminators
Fiber optic test equipment
Figure 1a. Electrical Interface
Figure 1b. Optical Interface
E4/STM-1/OC-3
OVERHEAD
PROCESSOR
OSC
S3031B
XCVR
XFMR
139.264/155.52 Mbps NRZ
139.264/155.52 Mbps NRZ
139.264/155.52 Mbps CMI
139.264/155.52 Mbps CMI
COAX
17.408/19.44 MHz
XFMR
COAX
DEVICE
SPECIFICATION
GENERAL DESCRIPTION
The S3031B transceiver chip is a fully integrated CMI
encoding transmitter and CMI decoding receiver. The
chip derives high speed timing and data signals for
SONET/SDH or PDH-based equipment. The circuit is
implemented using AMCC's proven Phase Locked Loop
(PLL) technology. Figures 1a and 1b show typical
network applications.
The S3031B has two independent VCOs which are
synchronized to the local NRZ transmitted data and the
received CMI data respectively. The chip can be used
with either a 19.44 MHz or a 38.88 MHz reference clock
when operated in the SONET/SDH OC-3 mode. In E4
mode the chip can be operated with a 17.408 MHz or a
34.816 MHz reference in support of existing system
clocking schemes. On-chip coded-mark-inversion (CMI)
encoding and decoding is provided for 139.264 Mbps
and 155.52 Mbps interfaces.
The low jitter PECL interface for the serial data inputs
and the PECL nibble clock interface guarantee com-
pliance with the bit-error rate requirements of the Bellcore
and ITU-T standards. The S3031B is packaged in a
0.65 mm pitch 100-pin PQFP/TEP.
The S3031B provides the major active components on-
chip for a coaxial cable interface, including analog
transformer driver circuitry and equalization interface
circuitry. Discrete controls permit separate selection of
CMI or NRZ operation and analog (coaxial copper) or
PECL (optical module) media interfaces. Both line
loopback and diagnostic local loopback operation are
supported.
E4/STM-1/OC-3
OVERHEAD
PROCESSOR
OSC
S3031B
XCVR
139.264/155.52 Mbps NRZ
139.264/155.52 Mbps NRZ
139.264/155.52 Mbps
139.264/155.52 Mbps
17.408/19.44 MHz
OTX
ORX
2
S3031B
E4/STM-1/OC-3 ATM TRANSCEIVER
August 19, 1999 / Revision D
SONET/SDH OVERVIEW
Synchronous Optical Network (SONET) is a standard
for connecting one fiber system to another at the op-
tical level. SONET, together with the Synchronous
Digital Hierarchy (SDH) administered by the ITU-T,
form a single international standard for fiber intercon-
nect between telephone networks of different coun-
tries. SONET is capable of accommodating a variety
of transmission rates and applications.
The SONET standard is a layered protocol with four
separate layers defined. These are:
Photonic
Section
Line
Path
Figure 2 shows the layers and their functions. Each
of the layers has overhead bandwidth dedicated to
administration and maintenance. The photonic layer
simply handles the conversion from electrical to opti-
cal and back with no overhead. It is responsible for
transmitting the electrical signals in optical form over
the physical media. The section layer handles the
transport of the framed electrical signals across the
optical cable from one end to the next. Key functions
of this layer are framing, scrambling, and error moni-
toring. The line layer is responsible for the reliable
transmission of the path layer information stream
carrying voice, data, and video signals. Its main func-
tions are synchronization, multiplexing, and reliable
transport. The path layer is responsible for the actual
transport of services at the appropriate signaling rates.
Data Rates and Signal Hierarchy
Table 1 contains the data rates and signal designa-
tions of the SONET hierarchy. The lowest level is the
basic SONET signal referred to as the synchronous
transport signal level-1 (STS-1). An STS-
N signal is
made up of
N byte-interleaved STS-1 signals. The
optical counterpart of each STS-
N signal is an optical
carrier level-
N signal (OC-N). The S3031B supports
OC-3 rates (155.52 Mbps).
Frame and Byte Boundary Detection
The SONET/SDH fundamental frame format for STS-3
consists of nine transport overhead bytes followed by
Synchronous Payload Envelope (SPE) bytes. This pat-
tern of 9 overhead and 261 SPE bytes is repeated
nine times in each frame. Frame and byte boundaries
are detected using the A1 and A2 bytes found in the
transport overhead. (See Figure 3.)
For more details on SONET operations, refer to the
Bellcore SONET standard document.
Elec.
ITU-T
Optical Data Rate (Mbps)
STS-1
OC-1
51.84
STS-3
STM-1
OC-3
155.52
STS-12
STM-4
OC-12
622.08
STS-24
OC-24
1244.16
STS-48
STM-16
OC-48
2488.32
Table 1. SONET Signal Hierarchy
9
Rows
9 x 261 =
2349 bytes
Transport Overhead
Synchronous Payload
Envelope
9 Columns
261 Columns
125
sec
v
v
1
A
1
A
1
A
2
A
2
A
2
A
0
J
0
Z
0
Z
1
B
*
*
1
E
*
*
1
F
*
*
1
D
*
*
2
D
*
*
3
D
*
*
1
H
1
H
1
H
2
H
2
H
2
H
3
H
3
H
3
H
2
B
2
B
2
B
1
K
*
*
2
K
*
*
4
D
*
*
5
D
*
*
6
D
*
*
7
D
*
*
8
D
*
*
9
D
*
*
0
1
D
*
*
1
1
D
*
*
2
1
D
*
*
1
S
1
Z
1
Z
2
Z
2
Z
1
M
2
E
*
*
Figure 3. STS-3/OC Frame Format
Figure 2. SONET Structure
0 bps
End Equipment
Payload to
SPE mapping
Maintenance,
protection,
switching
Optical
transmission
Scrambling,
framing
Fiber Cable
End Equipment
Section layer
Photonic layer
Line layer
Path layer
Path layer
Section layer
Photonic layer
Line layer
Layer Overhead
(Embedded Ops
Channel)
Functions
576 Kbps
192 Kbps
E4/STM-1/OC-3 ATM TRANSCEIVER
S3031B
3
August 19, 1999 / Revision D
S3031B OVERVIEW
The S3031B transceiver can be used to implement the
front end of STS-3, OC-3 or E4 equipment. The block
diagram in Figure 9 shows the basic operation of the
chip.
When the S3031B is operating in the nibble parallel
mode, the transmitter VCO is synchronized to the 38.88
MHz nibble clock as both the reference clock and the
data transfer clock. If the serial input is selected as the
transmitter data source the VCO will be synchronized
directly to the incoming data. Serial operation of the
S3031B transmitter section is possible with either the
38.88 MHz or 19.44 MHz reference oscillator. In the
absence of incoming serial data the transmitter section
will operate as a clock synthesizer. The receiver section
performs clock recovery by synchronizing its on-chip
VCO directly to the incoming data stream.
In E4 operation, the 34.816 MHz REFCLK is used as the
nibble clock. Thus in Nibble parallel mode, the S3031B
transmitter section supports unscrambled E4 operation.
If serial mode is selected, the NRZ E4 data must be
scrambled to allow the PLL to lock onto the data transi-
tions.
The S3031B provides a PECL output for an optical
interface and two transformer driver outputs for an
electrical interface. One of these drivers is a monitor
output. The S3031B provides a PECL input for an
optical interface and an analog input for an electrical
interface.
The transformer driver outputs are separately enabled.
Status outputs detect the disabled, stuck at 1, stuck at
0, and non-CMI states to qualify the transformer driver
outputs.
The CMI outputs, analog equalizer input section, and
PLL sections are independently powered for isolation
and for power savings when the device is used in single
function applications.
S3031B TRANSMITTER
ARCHITECTURE/FUNCTIONAL DESIGN
Transmitter Operation
The S3031B chip's transmitter section performs the last
stages of digital processing of a transmit SONET STS-3
or ITU-T E4 serial or 4-bit nibble parallel data stream.
Clock Recovery
If the serial input data has been selected, and serial
data is present at the TSDATIP/N inputs, the clock is
recovered from the serial data stream at 139.264 MHz
or 155.52 MHz and synthesized to 278.528 MHz or
311.04 MHz to CMI encode the incoming data.
In clock recovery mode, the transmitter PLL continues
to monitor the reference clock with respect to the VCO
and the activity of the serial data input. The transmitter
PLL will re-lock to the reference clock under the follow-
ing conditions:
1. If the serial data inputs contains insufficient transition
density (run length greater than 100 to 200 bit times).
2. If the VCO drifts away from the local reference clock
by more than 1000 ppm.
If either XFRMENA or XFRMENB are enabled (logic
Low) the density or frequency error defined above will
set the appropriate status (XFRMSTATA and/or
XFRMSTATB) to the low or fault state.
The selected drive status bits will return to the High or
clear state and the PLL will again lock to the data if the
serial data contains sufficient transition density (less
than 100 to 200 bit times between rising edges), and the
serial clock is within 250 ppm of the reference clock
determined frequency.
Optical and Electrical Interfaces
The digital data outputs (TSDATOP/N) are the PECL
outputs for an optical interface and are to be con-
nected to an electrical to optical converter, as shown
in Figure 17. This data is also routed to two on-chip
transformer drivers and sent out on XFRMDRVA and
XFRMDRVB to drive the transformers of the electri-
cal interface, as shown in Figure 19. These outputs
are shut off when the reset is active, XFRMEN is active,
or when the chip is in NRZ mode and the data inputs
are in the logic zero state. The electrical characteristics
for the transformer drivers are shown in Table 9.
4
S3031B
E4/STM-1/OC-3 ATM TRANSCEIVER
August 19, 1999 / Revision D
Parallel-to-Serial Converter
The parallel-to-serial converter shown in Figure 9 is
comprised of two 4-bit registers. The first register latches
the data from the PIN[3:0] bus on the rising edge of
REFCLK. The second register is a parallel loadable
shift register which takes its parallel input from the first
register.
The parallel data transfer between registers is accom-
plished on the falling edge of REFCLK. The serial data
is shifted out at the serial bit rate to the CMI encoder.
CMI Encoding
Coded Mark Inversion format (CMI) ensures at least
one data transition per 1.5 bit periods, thus aiding
the clock recovery process. Zeros are represented
by a Low state for one half a bit period, followed by a
High state for the rest of that bit period. Ones are
represented by a steady Low or High state for a full
bit period. The state of the ones bit period alternates
at each occurrence of a one. Figure 4 shows an
example of CMI-encoded data. The STS-3 electrical
interface and the E4 interface are specified to have
CMI-encoded data.
The CMI encoder on the S3031B accepts serial data
from TSDATIP/N at 139.264 or 155.52 Mb/s. The
data is then encoded into CMI format, and the result
is shifted out with transitions at twice the basic data
rate. The CMISEL input controls whether the CMI en-
coder is in the data path. A CMI code violation can be
inserted for diagnostic purposes by activating the
DLCV input. The DLCV input is sampled on every
cycle of the serial clock to allow the single or multiple
line code violations to be inserted. This violation is
either an inverted zero code or an inversion of the
alternating ones logic level, depending on the state of
the data. Subsequent one codes take into account the
induced violation to avoid error multiplication.
Figure 5. Jitter Generation Specifications
Compliant to G.823 and G.825
Figure 6. S3031B Maximum Allowable Input Jitter
f1
STM-1
500
f1(Hz)
E4
1. UI rms
2. UI pp
200
65
f2(kHz)
10
1.3
f3(MHz)
3.5
1.5
(2)
A1
1.5
(2)
0.15
(2)
OC-3
--
--
--
0.01
(1)
0.01
(1)
A2
0.075
(2)
A1
A2
f2
f3
500Hz
STM-1
65
f2(kHz)
E4
10
1. UI rms
2. UI pp
1.45
(2)
A1
1.45
(2)
0.10
(2)
OC-3
--
0.005
(1)
0.005
(1)
A2
0.025
(2)
A1
A2
f2
1.3 MHz
225 kHz
Slope = +20 dB/decade
Jitter Generation
Jitter Generation is defined as the amount of jitter at
the OC-3 or E-4 output of equipment. Jitter genera-
tion for OC-3 shall not exceed 0.01 UI rms when
measured using a highpass filter with a 12 kHz cutoff
frequency.
For STM-1 and E4, the jitter generated shall not ex-
ceed the specifications shown in Figure 5.
In order to meet the SONET, STM-1 E4 jitter specifica-
tions as shown in Figure 5, the TSDATIP/N serial data
input must meet the jitter characteristics as shown in
Figure 6.
Figure 4. CMI Encoded Data
A2
A1
t
0
0
1
0
1
1
1
0
E4/STM-1/OC-3 ATM TRANSCEIVER
S3031B
5
August 19, 1999 / Revision D
Figure 7. Mask of a pulse corresponding to a binary 0 Compliant to G.703
Notes:
1. The maximum "steady state" amplitude should not exceed the 0.55V limit. Overshoots and other transients are permitted to
fall into the dotted area, bounded by the amplitude levels 0.55V and 0.6V, provided that they do not exceed the steady state
level by more than 0.05V. The possibility of relaxing the amount by which the overshoot may exceed the steady state level
is under study.
2. For the purpose of these masks, the rise time and decay time should be measured between -0.4V and 0.4V, and should not
exceed 2 ns.
3. The inverse pulse in Figure 8 will have the same characteristics, noting that the timing tolerances at the zero level of the
negative and positive transitions are
0.1 ns and
0.5 ns respectively.
Figure 8. Mask of a pulse corresponding to a binary 1 Compliant to G.703
T=
7.18 ns for E4
6.43 ns for 155 CMI
T=
7.18 ns for E4
6.43 ns for 155 CMI
t =
1.35 ns for E4
1.20 ns for 155 CMI
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