1
S3038
SONET/SDH/ATM OC-12 QUAD TRANSCEIVER
September 16, 1999 / Revision B
BiCMOS LVPECL CLOCK GENERATOR
DEVICE
SPECIFICATION
SONET/SDH/ATM OC-12 TRANSMITTER AND RECEIVER
S3038
FEATURES
Complies with Bellcore and ITU-T
specifications
Supports 622.08 Mbps (OC-12)
Quad transmitter incorporating phase-locked
loop (PLL) clock synthesis from a low speed
reference clock
Quad receiver PLL provides clock and
data recovery
Selectable reference frequencies of 38.88
MHz, or 77.76 MHz
Interface to both LVPECL and TTL logic
8-bit TTL datapath
Compact 23mm x 23mm 208 TBGA package
Diagnostic loopback mode
Low jitter LVPECL interface
Single 3.3V supply
Local Loopback
APPLICATIONS
SONET/SDH-based transmission systems
SONET/SDH modules
SONET/SDH test equipment
ATM over SONET/SDH
Section repeaters
Add Drop Multiplexers (ADM)
Broad-band cross-connects
Fiber optic terminators
Fiber optic test equipment
SONET/SDH/ATM OC-12 QUAD TRANSCEIVER
S3038
GENERAL DESCRIPTION
The S3038 SONET/SDH Quad transceiver chip is a
fully integrated serialization/deserialization SONET
OC-12 (622.08 Mbit/s) interface device. The chip per-
forms all necessary serial-to-parallel and
parallel-to-serial functions in conformance with SO-
NET/SDH transmission standards. The device is
suitable for SONET-based ATM applications. Figure
1 shows a typical network application.
On-chip clock synthesis is performed by the high-
frequency phase-locked loop on the S3038 Quad
transceiver chip allowing the use of a slower external
transmit clock reference. Clock recovery is performed
on the device by synchronizing its on-chip VCO directly
to the incoming data stream. The S3038 also per-
forms SONET/SDH frame detection. The chip can be
used with a 38.88 MHz, or 77.76 MHz reference
clock, in support of existing system clocking
schemes.
The low jitter LVPECL interface guarantees compliance
with the bit-error rate requirements of the Bellcore
and ITU-T standards. The S3038 is packaged in a
23mm x 23mm 208 TBGA.
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S3038
SONET/SDH/ATM OC-12 QUAD TRANSCEIVER
September 16, 1999 / Revision B
Figure 1. System Block Diagram
Network
Interface
Processor
Network
Interface
Processor
8
8
8
8
SONET/SDH
Transceiver
A
SONET/SDH
Transceiver
A
OTX
ORX
OTX
ORX
2
2
2
OTX
ORX
2
2
2
OTX
ORX
2
2
8
8
8
8
SONET/SDH
Transceiver
B
SONET/SDH
Transceiver
B
OTX
ORX
OTX
ORX
2
2
2
OTX
ORX
2
2
2
OTX
ORX
2
2
8
8
8
8
SONET/SDH
Transceiver
C
SONET/SDH
Transceiver
C
OTX
ORX
OTX
ORX
2
2
2
OTX
ORX
2
2
2
OTX
ORX
2
2
8
8
8
8
SONET/SDH
Transceiver
D
SONET/SDH
Transceiver
D
OTX
ORX
OTX
ORX
2
2
2
OTX
ORX
2
2
2
OTX
ORX
2
2
S3038
S3038
3
S3038
SONET/SDH/ATM OC-12 QUAD TRANSCEIVER
September 16, 1999 / Revision B
Figure 2. S3038 Input/Output Diagram
8
8
8
8
8
8
8
8
REFCLK
RESET
PCLK
PINA[7:0]
PINB[7:0]
PINC[7:0]
PIND[7:0]
PICLKA
PICLKB
PICLKC
PICLKD
POCLKAP/N
FPA
POCLKBP/N
FPB
POCLKCP/N
FPC
POCLKDP/N
FPD
POUTA[7:0]
POUTB[7:0]
POUTC[7:0]
POUTD[7:0]
CH_LOCK
OOF
CLKSEL
TMODE
TSDA0P/N
TSDA1P/N
TSDB0P/N
TSDB1P/N
TSDC0P/N
TSDC1P/N
TSDD0P/N
TSDD1P/N
RSDA0P/N
RSDA1P/N
RSDB0P/N
RSDB1P/N
RSDC0P/N
RSDC1P/N
RSDD0P/N
RSDD1P/N
RSDASEL
RSDBSEL
RSDCSEL
RSDDSEL
DLEB
SDTTL
S3038
CAP1
CAP2
4
S3038
SONET/SDH/ATM OC-12 QUAD TRANSCEIVER
September 16, 1999 / Revision B
Figure 3. Transmitter Block Diagram
8
PINA[7:0]
TSDA1P
TSDA1N
TSDA0P
TSDA0N
TSDABP
8
Shift
Reg
8
PINB[7:0]
TSDB1P
TSDB1N
TSDB0P
TSDB0N
TSDBBP
8
Shift
Reg
PICLKB
8
PINC[7:0]
TSDC1P
TSDC1N
TSDC0P
TSDC0N
TSDCBP
8
Shift
Reg
PICLKC
8
PIND[7:0]
TSDD1P
TSDD1N
TSDD0P
TSDD0N
TSDDBP
8
Shift
Reg
PICLKD
TX PLL
8x/16x
REFCLK
CLKSEL
MUX
REFCLK
PCLK
FIFO
(input)
FIFO
(input)
FIFO
(input)
FIFO
(input)
PICLKA
0 1 2 3
CH_LOCK
0 1 2 3
0 1 2 3
0 1 2 3
CH_LOCK
PICLKB
PICLKC
TMODE
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S3038
SONET/SDH/ATM OC-12 QUAD TRANSCEIVER
September 16, 1999 / Revision B
Figure 4. Receiver Block Diagram
RX CRU
Serial-
Parallel
RX CRU
Serial-
Parallel
POUTA[7:0]
RSDA0P
RSDA0N
RSDA1P
RSDA1N
RSDASEL
SDTTLA
OOFA
RSDB0P
RSDB0N
RSDB1P
RSDB1N
RSDBSEL
SDTTLB
OOFB
POUTB[7:0]
Q
FIFO
(output)
RX CRU
Serial-
Parallel
POUTD[7:0]
RSDD0P
RSDD0N
RSDD1P
RSDD1N
RSDDSEL
DLEB
SDTTLD
OOFD
RX CRU
Serial-
Parallel
POUTC[7:0]
RSDC0P
RSDC0N
RSDC1P
RSDC1N
RSDCSEL
SDTTLC
OOFC
TSDDBP
TSDCBP
TSDBBP
TSDABP
REFCLK
8
8
8
8
POCLKAP/N
POCLKBP/N
POCLKCP/N
POCLKDP/N
FIFO
(output)
FIFO
(output)
FIFO
(output)
CH_LOCK
Receiver
Core A
Receiver
Core B
Receiver
Core C
Receiver
Core D
Framing
Data
Stretching
Timing
Framing
Data
Stretching
Timing
Framing
Data
Stretching
Timing
Framing
Data
Stretching
Timing
FPD
FPC
FPB
FPA
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