1
S3041
SONET/SDH/ATM OC-48 8:1 TRANSMITTER
January 7, 2000 / Revision G
BiCMOS LVPECL CLOCK GENERATOR
DEVICE
SPECIFICATION
SONET/SDH/ATM OC-12 TRANSMITTER AND RECEIVER
S3041
FEATURES
Micro-power Bipolar technology
Complies with Bellcore and ITU-T
specifications
On-chip high-frequency PLL for clock generation
Supports 2.488 GHz (OC-48)
Reference frequency of 155.52 MHz
8-bit LVDS data path
Compact 100 TQFP/TEP package
Diagnostic loopback mode
Line loopback
Lock detect
Low jitter LVPECL interface
Single 3.3V supply
APPLICATIONS
SONET/SDH-based transmission systems
SONET/SDH modules
SONET/SDH test equipment
ATM over SONET/SDH
Section repeaters
Add drop multiplexers
Broad-band cross-connects
Fiber optic terminators
Fiber optic test equipment
Figure 1. System Block Diagram
SONET/SDH/ATM OC-48 8:1 TRANSMITTER
S3041
GENERAL DESCRIPTION
The S3041 SONET/SDH Mux chip is a fully integrated
serialization SONET OC-48 (2.488 GHz) interface de-
vice. The chip performs all necessary parallel-to-serial
and clock synthesis functions in conformance with
SONET/SDH transmission standards. The device is
suitable for SONET-based ATM applications. Figure
1 shows a typical network application.
On-chip clock synthesis PLL components are con-
tained in the S3041 Mux chip allowing the use of a
slower external transmit clock reference. The chip
can be used with a 155.52 MHz reference clock, in
support of existing system clocking schemes.
The low jitter LVPECL interface guarantees compli-
ance with the bit-error rate requirements of the
Bellcore and ITU-T standards. The S3041 is pack-
aged in a 100 TQFP/TEP, offering designers a small
package outline.
Network Interface
Processor
S3045
S3041
S3042
S3042
S3041
OTX
ORX
OTX
ORX
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
Network Interface
Processor
S3045
S3040
S3040
2
S3041
SONET/SDH/ATM OC-48 8:1 TRANSMITTER
January 7, 2000 / Revision G
The sequence of operations is as follows:
Transmitter Operations:
1. 8-bit parallel input
2. Parallel-to-serial conversion
3. Serial output
Internal clocking and control functions are transpar-
ent to the user. Details of data timing can be seen in
Figures 7 through 10.
S3041 OVERVIEW
The S3041 Mux implements SONET/SDH serializa-
tion and transmission functions. The block diagram
in Figure 2 shows basic operation of the chip. This
chip can be used to implement the front end of
SONET equipment, which consists primarily of the
serial transmit interface and the serial receive inter-
face. The chip includes parallel-to-serial conversion
and system timing. The system timing circuitry con-
sists of a high-speed phase detector, clock dividers,
and clock distribution throughout the front end.
Figure 2. S3041 Functional Block Diagram
AMCC
S3040
OC-48 Clock Recovery Device
AMCC
S3045
OC-48 to OC-12 Demux
AMCC
S3042
OC-48 Demux
Suggested Interface Devices
M
U
X
M
U
X
16
PINP/N[7:0]
LLDP/N
LLCLKP/N
LLEB
8:1 PARALLEL
TO SERIAL
TSDP/N
LSDP/N
DLEB
PICLKP/N
TIMING
GEN
PCLKP/N
LOCKDET
VCO,
CLOCK DIVIDER and
PHASE DETECTOR
RSTB
D
TSCLKP/N
LSCLKP/N
TESTEN
REFCLKP/N
READP/N
PULSE0P/N
77MCK
KILLTXCLKN
CAP1/2
FIFO
3
S3041
SONET/SDH/ATM OC-48 8:1 TRANSMITTER
January 7, 2000 / Revision G
SONET OVERVIEW
Synchronous Optical Network (SONET) is a standard
for connecting one fiber system to another at the opti-
cal level. SONET, together with the Synchronous
Digital Hierarchy (SDH) administered by the ITU-T,
forms a single international standard for fiber inter-
connect between telephone networks of different
countries. SONET is capable of accommodating a
variety of transmission rates and applications.
The SONET standard is a layered protocol with four
separate layers defined. These are:
Photonic
Section
Line
Path
Figure 3 shows the layers and their functions. Each
of the layers has overhead bandwidth dedicated to
administration and maintenance. The photonic layer
simply handles the conversion from electrical to optical
and back with no overhead. It is responsible for
transmitting the electrical signals in optical form over
the physical media. The section layer handles the
transport of the framed electrical signals across the
optical cable from one end to the next. Key functions
of this layer are framing, scrambling, and error moni-
toring. The line layer is responsible for the reliable
transmission of the path layer information stream
carrying voice, data, and video signals. Its main
functions are synchronization, multiplexing, and reli-
able transport. The path layer is responsible for the
actual transport of services at the appropriate signaling
rates.
Figure 4 shows a standard OC-48 Frame former
structure.
Data Rates and Signal Hierarchy
Table 1 contains the data rates and signal designations
of the SONET hierarchy. The lowest level is the basic
SONET signal referred to as the synchronous transport
signal level-1 (STS-1). An STS-
N signal is made up of
N byte-interleaved STS-1 signals. The optical counter-
part of each STS-
N signal is an optical carrier level-N
signal (OC-
N). The S3041 chip supports OC-48 rate
(2.488 Gbps).
Elec.
CCITT
Optical Data Rate (Mbps)
STS-1
OC-1
51.84
STS-3
STM-1
OC-3
155.52
STS-12
STM-4
OC-12
622.08
STS-24
STM-8
OC-24
1244.16
STS-48 STM-16
OC-48 2488.32
Table 1. SONET Signal Hierarchy
Figure 3. SONET Structure
Figure 4. STS48/OC48 Frame Format
End Equipment
Payload to
SPE mapping
Maintenance,
protection,
switching
Optical
transmission
Scrambling,
framing
Fiber Cable
End Equipment
Section layer
Photonic layer
Line layer
Path layer
Path layer
Section layer
Photonic layer
Line layer
Functions
9 Rows
48 A1
Bytes
48 A2
Bytes
A1 A1
A1 A1
A2 A2
A2 A2
Transport Overhead 144 Columns
144 x 9 = 1296 bytes
Synchronous Payload Envelope 4176 Columns
4176 x 9 = 37,584 bytes
125
sec
s
s
4
S3041
SONET/SDH/ATM OC-48 8:1 TRANSMITTER
January 7, 2000 / Revision G
S3041 ARCHITECTURE/FUNCTIONAL
DESIGN
Mux Operation
The S3041 performs the serializing stage in the pro-
cessing of a transmit SONET STS-48 bit serial data
stream. It converts the byte serial 311 Mbyte/sec data
stream to bit serial format at 2.488 Gbps. Diagnostic
loopback is provided (transmitter to receiver), and Line
Loopback is also provided (receiver to transmitter).
A high-frequency bit clock is generated from a
155.52 MHz frequency reference by using a fre-
quency synthesizer consisting of an on-chip
phase-locked loop circuit with a divider.
Clock Divider and Phase Detector
The Clock Divider and Phase Detector, shown in the
block diagram in Figure 2, contains monolithic PLL
components.
The REFCLK input must be generated from a differ-
ential LVPECL crystal oscillator which has a
frequency accuracy of better than 20 ppm in order
for the VCOCLK frequency to have the same accu-
racy required for operation in a SONET system.
In order to meet the .01 UI SONET jitter specifica-
tions, the maximum reference clock jitter must be
guaranteed over the 12 KHz to 20 MHz bandwidth.
For details of reference clock jitter requirements, see
Table 2.
Timing Generator
The Timing Generator function, seen in Figure 2, pro-
vides two separate functions. It provides a byte rate
version of the TSCLK, and a mechanism for aligning
the phase between the incoming byte clock and the
clock which loads the parallel-to-serial shift register.
The PCLK output is a byte rate version of TSCLK.
For STS-48, the PCLK frequency is 311 MHz. PCLK
is intended for use as a byte speed clock for up-
stream multiplexing and overhead processing circuits.
Using PCLK for upstream circuits will ensure a
stable frequency and phase relationship between the
data coming into and leaving the S3041 device.
In the parallel-to-serial conversion process, the in-
coming data is passed from the PICLK byte clock
timing domain to the internally generated byte clock
timing domain, which is phase aligned to TSCLK.
The Timing Generator also produces a feedback ref-
erence clock to the Phase Detector. A counter divides
the synthesized clock down to the same frequency
as the reference clock REFCLK.
Parallel-to-Serial Converter
The FIFO is used to accomodate phase differences
between the internal byte clock and the external
PICLK. The READ and PULSE signals are used to
control the FIFO to prevent overflow/underflow con-
ditions.
The Parallel-to-Serial converter shown in Figure 2 is
comprised of a FIFO and a parallel-to-serial register.
The FIFO latches the data from the PIN[7:0] bus on
the rising edge of PICLK. The parallel-to-serial regis-
ter is a parallel loadable shift register which takes its
parallel input from the FIFO.
An internally generated byte clock, which is phase
aligned to the transmit serial clock as described in the
Timing Generator description, activates the parallel
data transfer between registers. The serial data is
shifted out of the second register at the TSCLK rate.
Table 2. Reference Jitter Limits
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SONET/SDH/ATM OC-48 8:1 TRANSMITTER
January 7, 2000 / Revision G
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u
o
r
ll
i
w
1
4
0
3
S
e
h
t
,
e
v
i
t
c
a
s
i
B
E
L
L
n
e
h
W
.
e
v
i
t
c
a
r
o
f
e
v
i
t
c
a
n
I
.
s
t
u
p
t
u
o
K
L
C
S
T
/
D
S
T
e
h
t
o
t
s
t
u
p
n
i
K
L
C
L
L
/
D
L
L
e
h
t
.
n
o
i
t
a
r
e
p
o
l
a
m
r
o
n
Table 3. Input Pin Assignment and Description
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