1
S3042
SONET/SDH/ATM OC-48 1:8 RECEIVER
June 24, 1999 / Revision E
BiCMOS LVPECL CLOCK GENERATOR
DEVICE
SPECIFICATION
SONET/SDH/ATM OC-12 TRANSMITTER AND RECEIVER
S3042
FEATURES
Micro-power Bipolar technology
Complies with Bellcore and ITU-T
specifications
Supports 2.488 Gbps (OC-48)
8-bit LVDS data path
Compact 100 TQFP/TEP package
Diagnostic loopback mode
Line loopback
LVPECL Signal detect input
Low jitter serial interface
Single 3.3V supply
APPLICATIONS
SONET/SDH-based transmission systems
SONET/SDH modules
SONET/SDH test equipment
ATM over SONET/SDH
Section repeaters
Add drop multiplexers
Broad-band cross-connects
Fiber optic terminators
Fiber optic test equipment
Figure 1. System Block Diagram
SONET/SDH/ATM OC-48 1:8 RECEIVER
S3042
GENERAL DESCRIPTION
The S3042 SONET/SDH receiver chip is a fully
integrated deserialization SONET OC-48 (2.488
Gbps) interface device. The chip performs all
necessary serial-to-parallel and framing functions
in conformance with SONET/SDH transmission
standards. The device is suitable for SONET-
based ATM applications. Figure 1 shows a typical
network application.
The low jitter serial interface guarantees compliance
with the bit-error rate requirements of the Bellcore
and ITU-T standards. The S3042 is packaged in a
100 TQFP/TEP, offering designers a small package
outline.
Network Interface
Processor
S3045
S3041
S3042
S3042
S3041
OTX
ORX
OTX
ORX
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
Network Interface
Processor
S3045
S3040
S3040
2
S3042
SONET/SDH/ATM OC-48 1:8 RECEIVER
June 24, 1999 / Revision E
The sequence of operations of the S3042 is as follows:
Receiver Operations:
1. Serial input
2. Frame detection
3. Serial-to-parallel conversion
4. 8-bit parallel output
Internal clocking and control functions are transpar-
ent to the user. Details of data timing can be seen in
Figures 7 through 9.
S3042 OVERVIEW
The S3042 receiver implements SONET/SDH
deserialization and frame detection functions. The
block diagram in Figure 2 shows basic operation of
the chip. This chip can be used to implement the
front end of SONET equipment, which consists pri-
marily of the serial transmit interface and the serial
receive interface. The chip includes serial-to-parallel
conversion and system timing. The system timing
circuitry consists of management of the datastream,
framing, and clock distribution throughout the front end.
Figure 2. S3042 Functional Block Diagram
AMCC
S3040
Clock Recovery Device
AMCC
S3045
OC-48 to OC-12 Mux/Demux
AMCC
S3041
OC-48 Mux
Suggested Interface Devices
1:8 SERIAL
TO PARALLEL
TIMING
GEN
M
U
X
RSDP/N
FRAME
BYTE
DETECT
DLEB
OOF
FRAMEN
FPP/N
SEARCH
KILLRXCLK
LLCLKP/N
LLDP/N
POUTP/N[7:0]
16
RSCLKP/N
LSCLKP/N
2
2
2
2
SDLVPECL
M
U
X
POCLKP/N
2
RX311MCKP/N
2
2
2
2
D
LLEB
RSTB
D
LSDP/N
3
S3042
SONET/SDH/ATM OC-48 1:8 RECEIVER
June 24, 1999 / Revision E
SONET OVERVIEW
Synchronous Optical Network (SONET) is a standard
for connecting one fiber system to another at the opti-
cal level. SONET, together with the Synchronous
Digital Hierarchy (SDH) administered by the ITU-T,
forms a single international standard for fiber inter-
connect between telephone networks of different
countries. SONET is capable of accommodating a
variety of transmission rates and applications.
The SONET standard is a layered protocol with four
separate layers defined. These are:
Photonic
Section
Line
Path
Figure 3 shows the layers and their functions. Each
of the layers has overhead bandwidth dedicated to
administration and maintenance. The photonic layer
simply handles the conversion from electrical to optical
and back with no overhead. It is responsible for
transmitting the electrical signals in optical form over
the physical media. The section layer handles the
transport of the framed electrical signals across the
optical cable from one end to the next. Key functions
of this layer are framing, scrambling, and error moni-
toring. The line layer is responsible for the reliable
transmission of the path layer information stream
carrying voice, data, and video signals. Its main
functions are synchronization, multiplexing, and reli-
able transport. The path layer is responsible for the
actual transport of services at the appropriate signaling
rates.
Data Rates and Signal Hierarchy
Table 1 contains the data rates and signal designations
of the SONET hierarchy. The lowest level is the basic
SONET signal referred to as the synchronous transport
signal level-1 (STS-1). An STS-
N signal is made up of
N byte-interleaved STS-1 signals. The optical counter-
part of each STS-
N signal is an optical carrier level-N
signal (OC-
N). The S3042 chip supports OC-48 rate
(2.488 Gbps).
Frame and Byte Boundary Detection
The SONET/SDH fundamental frame format for
STS-48 consists of 144 transport overhead bytes
followed by Synchronous Payload Envelope (SPE)
bytes. This pattern of 144 overhead and 4176 SPE
bytes is repeated nine times in each frame. Frame and
byte boundaries are detected using the A1 and A2
bytes found in the transport overhead. (See Figure 4.)
For more details on SONET operations, refer to the
Bellcore SONET standard document.
Elec.
CCITT
Optical Data Rate (Mbps)
STS-1
OC-1
51.84
STS-3
STM-1
OC-3
155.52
STS-12
STM-4
OC-12
622.08
STS-24
STM-8
OC-24
1244.16
STS-48 STM-16
OC-48 2488.32
Table 1. SONET Signal Hierarchy
Figure 3. SONET Structure
Figure 4. STS48/OC48 Frame Format
0 bps
End Equipment
Payload to
SPE mapping
Maintenance,
protection,
switching
Optical
transmission
Scrambling,
framing
Fiber Cable
End Equipment
Section layer
Photonic layer
Line layer
Path layer
Path layer
Section layer
Photonic layer
Line layer
Layer Overhead
(Embedded Ops
Channel)
Functions
576 Kbps
192 Kbps
9 Rows
48 A1
Bytes
48 A2
Bytes
A1 A1
A1 A1
A2 A2
A2 A2
Transport Overhead 144 Columns
144 x 9 = 1296 bytes
Synchronous Payload Envelope 4176 Columns
4176 x 9 = 37,584 bytes
125
sec
s
s
4
S3042
SONET/SDH/ATM OC-48 1:8 RECEIVER
June 24, 1999 / Revision E
RECEIVER OPERATION
The S3042 receiver chip provides the first stage of
digital processing of a receive SONET STS-48 bit-
serial stream. It converts the bit-serial 2.488 Gbps
data stream into a 311 Mbyte/sec byte-serial data for-
mat. A loopback mode is provided for diagnostic
loopback (transmitter to receiver). A Line Loopback
(receiver to transmitter) is also provided. Both line
and local loopback modes can be active at the same
time.
Frame and Byte Boundary Detection
The Frame and Byte Boundary Detection circuitry
searches the incoming data for three consecutive A1
bytes followed immediately by one A2 byte. Framing
pattern detection is enabled by the Out-of-Frame
(OOF) input. Detection is enabled by a rising edge on
OOF when FRAMEN is active. It is disabled when a
framing pattern is detected. When framing pattern de-
tection is enabled, the framing pattern is used to lo-
cate byte and frame boundaries in the incoming data
stream (RSD or looped transmitter data). During this
time, the parallel data bus (POUT [7:0]) will not con-
tain valid data. The timing generator block takes the
located byte boundary and uses it to block the incom-
ing data stream into bytes for output on the parallel
output data bus (POUT[7:0]). The frame boundary is
reported on the Frame Pulse (FP) output when any
32-bit pattern matching the framing pattern is de-
tected on the incoming data stream. When framing
pattern detection is disabled, the byte boundary is
frozen to the location found when detection was pre-
viously enabled. Only framing patterns aligned to the
fixed byte boundary are indicated on the FP output.
Frame detection can be immediately disabled by
bringing FRAMEN inactive.
The probability that random data in an STS-48
stream will generate the 32-bit framing pattern is ex-
tremely small. It is highly improbable that a mimic
pattern would occur within one frame of data. There-
fore, the time to match the first frame pattern and to
verify it with down-stream circuitry, at the next occur-
rence of the pattern, is expected to be less than the
required 250
s, even for extremely high bit error
rates.
Serial-to-Parallel Converter
The Serial-to-Parallel Converter consists of three
8-bit registers. The first is a serial-in, parallel-out
shift register, which performs serial to parallel con-
version clocked by the clock recovery block. The
second is an 8-bit internal holding register, which
transfers data from the serial to parallel register on
byte boundaries as determined by the frame and
byte boundary detection block. On the falling edge of
the POCLK, the data in the holding register is trans-
ferred to an output holding register which drives
POUT[7:0].
OTHER OPERATING MODES
Diagnostic Loopback
When the Diagnostic Loopback Enable (DLEB) input
is low, a loopback from the transmitter (S3041) to
the receiver (S3042) at the serial data rate can be
set up for diagnostic purposes. The differential serial
output data and clock from the transmitter (S3041)
(LSD/LSCLK) is routed to the receiver (S3042) (LSD/
LSCLK) in place of the normal data stream.
Line Loopback
The line loopback circuitry consists of alternate clock
and data output drivers. For the S3042, enabling line
loopback enables the LLD/LLCLK outputs. When the
line loopback enable input (LLEB) is inactive, the LLD/
LLCLK outputs are disabled. When LLEB is active,
data and clock from the primary inputs (RSD/RSCLK)
are transmitted on LLD/LLCLK, allowing a receive-to-
transmit loopback to be established at the serial data
rate. The S3042 LLD/LLCLK outputs should be con-
nected to the S3041 LLD/LLCLK inputs.
5
S3042
SONET/SDH/ATM OC-48 1:8 RECEIVER
June 24, 1999 / Revision E
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Table 2 . Input Pin Assignment and Descriptions
6
S3042
SONET/SDH/ATM OC-48 1:8 RECEIVER
June 24, 1999 / Revision E
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Table 3. Output Pin Assignment and Descriptions
7
S3042
SONET/SDH/ATM OC-48 1:8 RECEIVER
June 24, 1999 / Revision E
e
m
a
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8
3
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C
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3
,
2
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1
5
,
8
4
d
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t
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n
n
o
C
t
o
N
Table 4. Common Pin Assignment and Description
8
S3042
SONET/SDH/ATM OC-48 1:8 RECEIVER
June 24, 1999 / Revision E
1
2
3
4
5
6
7
8
9
10
11
26
27
28
29
30
31
32
33
34
82
81
63
62
61
60
59
58
57
56
S3042
Pinout
Top View
RSDP
RSDN
PECLVCC
PECLGND
PECLGND
RSCLKP
RSCLKN
COREVCC
COREGND
COREVCC
COREGND
COREVCC
COREGND
COREGND
TTLVCC
POUTN3
POUTP3
POUTN2
POUTP2
POUTN1
POUTP1
POUTN0
POUTP0
FPN
FPP
RX311MCKN
LVDSGND
LVDSGND
35
36
37
RX311MCKP
LVDSGND
LVDSGND
84
83
PECLVCC
PECLGND
PECLGND
PECLVCC
LLCLKN
LLCLKP
COREGND
COREGND
COREVCC
LSDN
LSDP
PECLVCC
PECLGND
PECLGND
PECLVCC
12
13
NC
NC
COREVCC
COREVCC
COREGND
COREGND
LVDSVCC
LVDSVCC
LVDSGND
LVDSGND
POCLKN
POCLKP
14
15
16
POUTN7
100 TQFP/TEP
POUTP7
PECLGND
TTLVCC
NC
POUTN5
POUTN6
POUTP6
POUTN4
POUTP5
PECLGND
PECLGND
LLDN
LLDP
PECLVCC
PECLVCC
PECLGND
PECLGND
LVDSVCC
LVDSVCC
SEARCH
RSTB
17
18
19
20
38
39
40
41
42
43
44
45
75
74
73
72
71
70
69
68
67
66
65
64
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
21
LVDSVCC
POUTP4
LVDSVCC
LVDSGND
LVDSGND
22
23
24
25
DLEB
LLEB
NC
TTLGND
TTLGND
46
47
48
49
50
55
54
53
52
51
OOF
FRAMEN
KILLRXCLK
SDLVPECL
NC
77
76
79
78
PECLGND
PECLVCC
PECLVCC
LSCLKN
LSCLKP
80
Figure 5. S3042 Pinout
9
S3042
SONET/SDH/ATM OC-48 1:8 RECEIVER
June 24, 1999 / Revision E
Figure 6. 100 TQFP/TEP Package
TOP VIEW
e
c
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P
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a
j
2
4
0
3
S
W
1
1
.
1
W
/
C
3
3
Thermal Management
10
S3042
SONET/SDH/ATM OC-48 1:8 RECEIVER
June 24, 1999 / Revision E
Table 5. Differential Low Swing CML Output DC Characteristics
s
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Table 6. Internally Biased LVPECL Input DC Characteristics
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1
Table 7. Externally Biased LVPECL Input DC Characteristics
s
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0
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2
1
11
S3042
SONET/SDH/ATM OC-48 1:8 RECEIVER
June 24, 1999 / Revision E
Table 9 Recommended Operating Conditions
l
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2
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V
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x
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4
=
Table 11. LVTTL Input/Output DC Characteristics
r
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m
Table 8. Absolute Maximum Ratings
1. Human body model.
Table 10. Power Consumption
1. Add 60 mA for line loopback active.
12
S3042
SONET/SDH/ATM OC-48 1:8 RECEIVER
June 24, 1999 / Revision E
l
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Table 12. LVDS Input/Output Characteristics
1
1. Output loading is 275
to GND and 100
line-to-line.
2. See Figure 13.
13
S3042
SONET/SDH/ATM OC-48 1:8 RECEIVER
June 24, 1999 / Revision E
Table 13. AC Receiver Timing Characteristics
Figure 7. Output Timing Diagram
Figure 8. Receiver Input Timing Diagram
Notes on High-Speed LVPECL Input Timing:
1. Timing is measured from the cross-over point of the reference signal to the cross-over point of the input.
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Figure 9. LLD Output Timing
tS
POUT
tP
POUT
tH
POUT
POCLK
POUT[7:0], FP
tS
RSD
tH
RSD
RSD/LSD
RSCLKP/LSCLKP
LLD
LLCLKP
tP
LLD
tH
LLD
tS
LLD
Notes on LVDS Output Timing:
1. Timing is measured from the cross-over point of the reference signal to the cross-over point of the output.
1. Timing is measured from the cross-over point of the reference signal to the cross-over point of the output.
14
S3042
SONET/SDH/ATM OC-48 1:8 RECEIVER
June 24, 1999 / Revision E
RECEIVER FRAMING
Figure 10 shows a typical reframe sequence in
which a byte realignment is made. The frame and
byte boundary detection is enabled by the rising
edge of OOF. The byte alignment is made during the
A1 data sequence, resulting in correct byte align-
ment on the outgoing data bus (POUT[7:0]). Frame
boundary is recognized upon receipt of the first A2
byte, and is reported via the frame pulse being set
high for one POCLK cycle concurrent with the third
A2 byte.
The frame and byte boundary detection block is acti-
vated by the rising edge of OOF, and stays active until
the first FP pulse.
Figure 11 shows the frame and byte boundary detection
activation by a rising edge of OOF, and deactivated by
the first FP pulse.
Figure 12 shows the frame and byte boundary detec-
tion activation by a rising edge of FRAMEN, and
deactivated by the FRAMEN input.
Figure 12 also shows the frame and byte boundary
detection activation by a rising edge on FRAMEN,
and deactivation by the first FP pulse.
Figure 10. Frame and Byte Detection
Invalid Data
Valid Data
A1
A1
A1
A1
A2
A2
A2 (28H)
15
S3042
SONET/SDH/ATM OC-48 1:8 RECEIVER
June 24, 1999 / Revision E
Figure 11. OOF Timing (FRAMEN = 1)
BOUNDARY DETECTION ENABLED
OOF
FP
SEARCH
Figure 12. FRAMEN Timing (OOF = 1)
Figure 13. Differential Voltage Measurement
V SINGLE
Single-ended
swing
V DIFF
2X Single-ended
swing
=
FP
SEARCH
FRAMEN
BOUNDARY
DETECTION
ENABLED
BOUNDARY
DETECTION
ENABLED
16
S3042
SONET/SDH/ATM OC-48 1:8 RECEIVER
June 24, 1999 / Revision E
Figure 14. +5V Differential PECL Driver to S3042 Input AC Coupled Termination
Figure 15. S3040 to S3042/S3044 Terminations
Vcc -.65V
Vcc -.65V
S3042/44
RSDP/N
RSCLKP/N
+5V
330
330
100
.01
F
.01
F
+3.3V
+5V
S3040
SERDATOP/N
SERCLKOP/N
+3.3V
S3042/44
RSDP/N
RSCLKP/N
.01
F
Vcc -.65V
.01
F
100
Vcc -.65V
17
S3042
SONET/SDH/ATM OC-48 1:8 RECEIVER
June 24, 1999 / Revision E
Figure 16. S3041 to S3042 for Diagnostic Loopback
Figure 17. S3042 LVDS Driver to S3045 LVDS Driver
Figure 18. S3040/48/50 +5V PECL Output to CML Input AC Coupled Termination
+3.3V
S3042
LSDP/N
LSCLKP/N
+3.3V
100
S3041
LSDP/N
LSCLKP/N
+3.3V
275
275
S3045
311 DATIN
311CLKIN
+3.3V
100
S3042
POCLK
POUT
+5V
S3040/48/50
SERDATO
SERCLKO
+5V
S3042/44
RSD
RSCLK
.01
F
Vcc -.65V
(DC AVG)
.01
F
100
Vcc -.65V
(DC AVG)
18
S3042
SONET/SDH/ATM OC-48 1:8 RECEIVER
June 24, 1999 / Revision E
Ordering Information
AMCC is a registered trademark of Applied Micro Circuits Corporation.
Copyright 1999 Applied Micro Circuits Corporation
AMCC reserves the right to make changes to its products or to discontinue any semiconductor product or service without notice, and
advises its customers to obtain the latest version of relevant information to verify, before placing orders, that the information being relied
on is current.
AMCC does not assume any liability arising out of the application or use of any product or circuit described herein, neither does it
convey any license under its patent rights nor the rights of others.
AMCC reserves the right to ship devices of higher grade in place of those of lower grade.
AMCC SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR
USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS.
Applied Micro Circuits Corporation 6290 Sequence Dr., San Diego, CA 92121
Phone: (858) 450-9333 (800) 755-2622 Fax: (858) 450-9885
http://www.amcc.com
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