1
S3045
SONET/SDH OC-48 TO OC-12 MUX/DEMUX EVALUATION BOARD
S3045
SONET/SDH OC-48 TO OC-12 MUX/DEMUX EVALUATION BOARD
DESCRIPTION
The S3045 Evaluation Board provides a flexible platform for verifying the operation of the S3045 with a SONET
tester. This user's manual provides information on the board contents.
Figure 1 shows the outline of the S3045 Evaluation Board. In Figure 2, the block diagram of how the S3045
Evaluation Board should be connected to the test equipment for SONET/SDH testing is shown. The four
possible test configurations are:
1.Use both the input/output on board clock recovery devices (S3040 #1, #2).
2.Use the input on board clock recovery device (S3040 #1).
3.Use the output on board clock recovery device (S3040 #2).
4.Do not use any of the on board clock recovery devices.
Figures 4-7, show the wiring connections for these four test setups.
The SONET network tester compares the received data with the transmitted data to determine whether an error
has occurred. The SONET tester can also demonstrate the SONET protocol features of the chipset. In addition,
most SONET testers should be able to manipulate any bits being transmitted to the S3045 test board to verify
the operation of SONET overhead and alarm functionality.
Required Parts:
The tests can be conducted using a SONET Tester and the Unit Under Test ( the S3045 Evaluation Board). The
following is a parts list of the items that will be needed.
1.Power cable between the power source and the S3045.
2.S3045 Test Board.
3.One 5 volt power supply (Current rating 2 Amps).
4.SONET/SDH network tester.
5.50 Ohm SMA terminated test cables.
6.Optional: 5.2V DC supply for VBB as required for SONET termination pulldowns.
Power Connections
Terminal posts are provided at the top edge of the board for VCC (+5V), and GND. The required +5V power
supply connected to the board provides the 5 volts for the S3040's. The board contains two power regulators
with one providing the 3.3 volts for the S3045, and the other supplying the 3.3 volts for the S3041 and S3042.
Figure 3 demonstrates the input and output LVPECL waveforms that the S3045 Evaluation Board will output.
(Note that in the final design of the S3045 Evaluation Board, the regulator providing 3.0V and 4.1V will be
modified to supply 3.3V by replacing R2 and R12.)
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S3045
SONET/SDH OC-48 TO OC-12 MUX/DEMUX EVALUATION BOARD
Figure 1. Test Board Layout
SERDATOP
SERDATIP
SERDATIN
SERDATON
SERCLKOP
SERCLKON
SERDATIP
SERDATOP
SERDATON
SERDATIN
S3040
#1
RSCLKN
RSDN
RSCLKP
SERCLKON
SERCLKOP
RSDP
TSDN
TSCLKP
TSCLKN
TSDP
S3045
45_DSCRBENB
45_SQUELCH
42_FRAMEN
42+KILLRXCLK
41_TESTEN
42_LLEB
45_PARFPTXSEL
45_J0/Z0SEL
45_B2/M1SEL
45_SCRBENB
45_B1SEL
45_PARSEL
45_PARFPRXSEL
45_FPSEL
41_LLEB
41_KILLCLK
"0"
"1"
"0"
"1"
POUTA[5]
POUTA[4]
POUTA[1]
POUTA[3]
POUTA[2]
POUTA[0]
POUTA[7]
POUTA[6]
FPA
PAROUTA
POUTD[2]
POUTD[3]
POUTD[6]
POUTD[4]
POUTD[5]
POUTD[7]
POUTD[0]
POUTD[1]
FPD
PAROUTD
POUTB[5]
POUTB[4]
POUTB[1]
POUTB[3]
POUTB[2]
POUTB[0]
POUTB[7]
POUTB[6]
FPB
PAROUTB
POUTC[5]
POUTC[4]
POUTC[1]
POUTC[3]
POUTC[2]
POUTC[0]
POUTC[7]
POUTC[6]
FPC
PAROUTC
LED'S
+5V
GND
3.0V POWER
REGULATOR
FOR S3041/42
3.3V POWER
REGULATOR
FOR S3045
S3042
S3041
S3040
#2
OOF
LOF
LOS
B1ERR
VBB
RESET
155CLKN
155CLKP
155CLKN
155CLKP
1
2
3
208
207
3
2
1
32
31
100
99
100
99
3
2
1
1
2
3
1
2
3
32
31
D4
D5
D6
D11
S1
J5
J6
J14
J13
S2
S3
J30
J28
U4
U2
J16
J15
AMCC S3045 Board B REV
S3040 #1
S3040 #2
U1
U3
U5
J23
J25
J26
J24
LOW/HIGH
45_SDPECL
EXT/INT
VBB_BIAS
J27
X1
X2
JP5
VR2
VR1
LOW/HIGH
40_SDPECL
JP4
JP8
J10
J9
J12
J11
J4
J3
J2
J1
J17
J18
J8
J7
J22
J21
J19
J20
155MHZ OSCILLATOR
155MHZ OSCILLATOR
JP2
INT 155
EXT 155
JP1
INT 155
EXT 155
REF/INT
LOCK
JP6
INT/REF
LOCK
JP7
J29
*
*
*
*
Not installed on single-ended configuration.
Programing FPGA
Installed however not used in single-ended operation.
The S3040 #2 is always configured for
differential applications.
1 2 3
3 2 1
1 2 3
1
3
5
2
4
6
1 2 3
1 2 3
5
3
1
6
4
2
(4.1V for
sampled
parts)
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S3045
SONET/SDH OC-48 TO OC-12 MUX/DEMUX EVALUATION BOARD
VBB should be 5.2V for tester outputs that require DC pulldown for activation. Otherwise, VBB should remain
open, or connected to ground as shown in Table 2, jumper JP8. Figure 2 depicts how the S3045 Evaluation
Board can be connected for SONET/SDH measurements, and shows all of the DIP switch settings, and the
LVPECL power supply requirements. This is accomplished by setting the VBB Bias voltage from an external
voltage supply. For SONET testers that need 50 Ohm's to 2V, set VBB Bias to -5.2V. External test equipment
with standard LVPECL or PECL may interface to the S3045 Evaluation Board, as indicated in Figure 3.
Figure 2. Test Setup (Differential Version Shown)
Figure 3. LVPECL and PECL Voltage Swing
Table 1. Power Connections for DUT and Test Equipment Interface
SONET TESTER *
S3040/41/42/45
DATA
DATA
SERDATIP
SERDATIN
DATA
TSDP
TSDN
TSCLKP
TSCLKN
CLOCK
CLOCK
270 Ohm
VBB
- HP Series 90
- ANRITSU MPE 3660
- W & G ANT-20E
- Or equivalent
*
Default Dip Switch Settings:
3 45_DSCRBENB
5 45_SQUELCH
5 42_KILLRXCLK
6 42_LLEB
7 45_PARFPTXSEL
8 45_J0/S0SEL
4 45_B2/M1SEL
2 45_SCRBENB
6 45_B1SEL
1 45_PARSEL
8 45_PARFPRXSEL
7 45_FPSEL
3 41_LLEB
2 41_KILLCLK
1 41_TESTEN
4 42_FRAMEN
VBB = -5.2V, ground, or open
VCC = +5V +/-5%
POWER SUPPLY
DATA
+5v
+3.3V
S3045
VBB or Open
"0"
"1"
"1"
"1"
"1"
"1"
Voltage
Regulators
S3040
S3041/42
+3.3V
270 Ohm
S2
S3
"1"
"1"
"1"
"1"
"1"
"0"
"0"
"1"
"0"
"0"
LVPECL
VCC to the board = +5V +/- 5%
2.5V
2V
1.5V
GND = 0V
Termination = 50 Ohms to (VCC -2V)
S3041 and S3042 SMA I/O Connections
PECL
VCC to the board = +5V +/- 5%
4.2V
3.7V
3.2V
S3040 SMA I/O Connections
y
l
p
p
u
S
r
e
w
o
P
e
g
a
t
l
o
V
t
u
p
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I
l
a
n
i
m
o
N
C
C
V
V
5
+
D
N
G
V
0
)
l
a
n
o
i
t
p
o
(
B
B
V
N
E
P
O
/
D
N
G
/
V
2
.
5
-
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S3045
SONET/SDH OC-48 TO OC-12 MUX/DEMUX EVALUATION BOARD
The user may vary VBB Bias (JP8) to terminate the S3045 Evaluation Board to different bias levels (VBB or
ground) as shown in Table 2. AC termination is part of the S3042 and S3040 inputs.
The user has the option of using one, both, or none of the on board clock recovery units (S3040).
The user can choose one of the following reference clock options for the S3040's:
1.An external single ended 155MHz (Default factory configuration).
2.An external differential 155 MHz (Must be configured at the factory for this option).
3.The on board 155MHz oscillator (Must be configured at the factory for this option).
JP1 and JP2 of the S3045 Evaluation Board must be configured as in Table 2 for the desired clock option.
SMA Edge Connectors.
SMA edge connectors are provided for the differential serial input/output signals and output clock. All interfaces
to the S3045 Evaluation Board are AC coupled, 50 Ohms.
S3040 #1
Serial Data In [SERDATIP/N] (J5, J6) (Internal Termination.) Clock is recovered from the transitions on these
inputs. J6 is not installed for a single-ended configuration.
Serial Data Out [SERDATOP/N] (J13, J14) This signal is the delayed version of the incoming data stream
(SERDATIP/N) updated on the falling edge of Serial Clock Out (SERCLKOP).
Serial Clock Out [SERCLKOP/N] (J15, J16) This signal is phase aligned with Serial Data Out (SERDATOP/N).
S3040 #2
Serial Data In [SERDATIP/N] (J7, J8) (Internal Termination.) Clock is recovered from the transitions on these
inputs.
Serial Data Out [SERDATOP/N] (J17, J18) This signal is the delayed version of the incoming data stream
(SERDATIP/N) updated on the falling edge of Serial Clock Out (SERCLKOP).
Serial Clock Out [SERCLKOP/N] (J19, J20) This signal is phase aligned with Serial Data Out (SERDATOP/N).
S3041
Transmit Clock Output [TSCLKP/N] (J11, J12) Transmit serial clock that can be used to retime the TSD
signal. An optical transmitter can use the rising edge of TSCLK to retime the TSD data.
Transmit Serial Data [TSDP/N] (J9, J10) Serial data stream signals, normally connected to an optical
transmitter module.
S3042
Receive Serial Data [RSDP/N] (J1, J2) Serial data streams normally connected to an optical module. These
inputs are clocked by the rising edge RSCLKP inputs. The RSD will be frame aligned and demultiplexed to an 8-
bit parallel output <7:0>. J2 is not installed for a single-ended configuration.
Receive Serial Clock [RSCLKP/N] (J3, J4) Recovered clock signal that is synchronous with the RSDP/N
inputs. This clock is used by the receive section as the master clock to perform framing and deserialization
functions. J4 is not installed for a single-ended configuration.
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S3045
SONET/SDH OC-48 TO OC-12 MUX/DEMUX EVALUATION BOARD
Dip Switch Settings
The S3045 Evaluation Board is equipped with two DIP switch modules (S2 and S3), to control the static control
functions of the on-board devices. For these DIP switches the OFF (open = "1") condition asserts a logic low on
the assigned signal, and the ON (closed = "0") condition asserts a logic high.
S1:
RESET Toggle Switch This momentary contact switch controls the master reset for the S3041/42/45.
S2:
Parity Select [45_PARSEL] When high selects even parity. When low selects odd parity.
Scramble Enable [45_SCRBENB] When low the frame synchronous scrambler is enabled. When high the
scrambler is disabled.
Descrambler Enable [45_DSCRBENB] When low the frame synchronous descrambler is enabled. When high
the frame synchronous descrambler is disabled.
B2/M1 Parity Byte and Parity count select [45_B2/M1SEL] When high the B2/M1 byte calculations and
insertions are disabled. When low B2 and M1 calculations and insertions are enabled.
Squelch Clock Mode [45_SQUELCH] Active low. Set inactive when a clock recovery device used provides a
continuous clock during signal loss or reacquisition. Set active when the clock recovery device used does not
provide a continuous clock during signal loss or signal acquisition. When active and SDLVPECL/SDLVTTL is
inactive, the transmitter serial clock (311TCLK) will be used to maintain timing in the receiving section. When
active and SDLVPECL/SDLVTTL is also active, the 311CLKIN is used for all receiver timing. When active there
is a 3.2 ns shortening or lengthening of the POCLK cycle.
B1 Parity Byte Select [45_B1SEL] When low B1 calculation and insertion is enabled. When high B1
calculation and insertion is disabled.
Frame Pulse Select [45_FPSEL] For normal board operation set low. When low the FRAME input is used to
generate the FP A,B,C,D pulse when the third A2 byte is output. When high the FP A,B,C,D output is internally
generated using the A1A2 frame boundary. The FP A,B,C,D is asserted high when the third A2 (28h) byte is
output.
Section-Trace Insertion Select [45_J0/Z0SEL] Select pins, select section-trace bytes J0/Z0 options. When
low the J0/Z0 bytes are passed through with no modification. When high byte 1 of 48 (J0 bytes) is passed
through with no modification (transparent) and bytes 2 through 48 (Z0 bytes) are filled with the values of 02hex
to 30hex (48 decimal) respectively.
S3:
Test Clock Enable [41_TESTEN] For normal board operation set high. When high this input will select the
LLCLK input instead of the internally generated 2.4 GHz clock as the system clock. When this input is Low it will
select the internally generated 2.4 GHz clock from the LLCLK input.
Kill Transmit Clock Input [41_KILLTXCLKN] For normal board operation set high. When low this input will
force the PCLKP/N and PULSE0P/N outputs low.
Line Loopback Enable [41_LLEB] For normal board operation set high. Selects Line Loopback when low.
When LLEB is low the S3041 will force the data from the LLD/LLCLK inputs from the S3042 to the TSD/TSCLK
outputs of the S3042.
Frame Enable Input [42_FRAMEN] For normal board operation set FRAMEN high. This enables the frame
detector circuit to detect A1 A2 alignment and lock to word boundary. When this input is low it will disable the
frame detector circuit and it will lock on the last byte alignment state.
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